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Número de pieza | MTV32N25E | |
Descripción | Power Field Effect Transistor | |
Fabricantes | ON Semiconductor | |
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Designer’s™ Data Sheet
TMOS E−FET.™
Power Field Effect
Transistor
D3PAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
The D3PAK package has the capability of housing the largest chip
size of any standard, plastic, surface mount power semiconductor. This
allows it to be used in applications that require surface mount
components with higher power and lower RDS(on) capabilities. This
high voltage MOSFET uses an advanced termination scheme to provide
enhanced voltage−blocking capability without degrading performance
over time. In addition, this advanced TMOS E−FET is designed to
withstand high energy in the avalanche and commutation modes. The
new energy efficient design also offers a drain−to−source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in surface mount PWM motor controls and both ac−dc and
dc−dc power supplies. These devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Short Heatsink Tab Manufactured − Not Sheared
• Specifically Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm, 13−inch/500 Unit Tape & Reel, Add −RL Suffix
to Part Number
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TMOS POWER FET
32 AMPERES, 250 VOLTS
RDS(on) = 0.08 W
D3PAK Surface Mount
CASE 433−01
Style 2
D
N−Channel
®G
S
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 1
1
Publication Order Number:
MTV32N25E/D
1 page MTV32N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to
the on−state when calculating td(off).
be charged by current from the generator.
At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for
complicate the analysis. The inductance of the MOSFET
calculating rise and fall because drain−gate capacitance
source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate
which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate
produces a voltage at the source which reduces the gate
of average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
During the turn−on and turn−off delay times, gate current is
inductive; the data in the figure is taken with a resistive load,
not constant. The simplest calculation uses appropriate
which approximates an optimally snubbed inductive load.
values from the capacitance curves in a standard equation
Power MOSFETs may be safely operated into an inductive
for voltage change in an RC network. The equations are:
load; however, snubbing reduces switching losses.
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
8000
7000
VDS = 0 V
Ciss
6000
VGS = 0 V
TJ = 25°C
5000
4000
3000 Crss
Ciss
2000
1000
0
−10
−5 0
5
VGS VDS
Coss
Crss
10 15 20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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5
5 Page V
P
U
L 2 PL
MTV32N25E
PACKAGE DIMENSIONS
CASE 433−01
ISSUE B
B
SQ
4
−T−
SEATING
PLANE
C
E
R
NA
12
G
3K
F
J
D 2 PL
H
0.13 (0.005) M T
X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
W
A 0.588 0.592 14.94 15.04
B 0.623 0.627 15.82 15.93
C 0.196 0.200 4.98 5.08
D 0.048 0.052 1.22 1.32
Y E 0.058 0.062 1.47 1.57
F 0.078 0.082 1.98 2.08
G 0.430 BSC
1.092 BSC
H 0.105 0.110 2.67 2.79
J 0.018 0.022 0.46 0.56
K 0.150 0.160 3.81 4.06
L 0.058 0.062 1.47 1.57
N 0.353 0.357 8.97 9.07
P 0.078 0.082 1.98 2.08
Q 0.053 0.057 1.35 1.45
R 0.623 0.627 15.82 15.93
S 0.313 0.317 7.95 8.05
U 0.028 0.032 0.71 0.81
V 0.050 −−− 1.27 −−−
W 0.054 0.058 1.37 1.47
X 0.050 0.060 1.27 1.52
Y 0.104 0.108 2.64 2.74
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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11
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For additional information, please contact your local
Sales Representative
MTV32N25E/D
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