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PDF MTB15N06V Data sheet ( Hoja de datos )
| Número de pieza | MTB15N06V | |
| Descripción | Power Field Effect Transistor | |
| Fabricantes | ON Semiconductor | |
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MTB15N06V
Designer’s™ Data Sheet
TMOS V™
Power Field Effect
Transistor
D2PAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
TMOS V is a new technology designed to achieve an on−resistance
area product about one−half that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50 and 60
volt TMOS devices. Just as with our TMOS E−FET designs, TMOS V
is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed switching
applications in power supplies, converters and power motor controls,
these devices are particularly well suited for bridge circuits where
diode speed and commutating safe operating areas are critical and
offer additional safety margin against unexpected voltage transients.
New Features of TMOS V
• On−resistance Area Product about One−half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E−FET Predecessors
Features Common to TMOS V and TMOS E−FETs
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E−FET
• Surface Mount Package Available in 16 mm 13−inch/2500 Unit Tape
& Reel, Add T4 Suffix to Part Number
http://onsemi.com
TMOS POWER FET
15 AMPERES, 60 VOLTS
RDS(on) = 0.12 W
D2PAK
CASE 418B−02,
Style 2
D
G
TM
S
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 3
1
Publication Order Number:
MTB15N06V/D
1 page  
MTB15N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to
the on−state when calculating td(off).
be charged by current from the generator.
At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for
complicate the analysis. The inductance of the MOSFET
calculating rise and fall because drain−gate capacitance
source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate
which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate
produces a voltage at the source which reduces the gate
of average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
During the turn−on and turn−off delay times, gate current is
inductive; the data in the figure is taken with a resistive load,
not constant. The simplest calculation uses appropriate
which approximates an optimally snubbed inductive load.
values from the capacitance curves in a standard equation
Power MOSFETs may be safely operated into an inductive
for voltage change in an RC network. The equations are:
load; however, snubbing reduces switching losses.
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1500
VDS = 0 V
1200 Ciss
VGS = 0 V
TJ = 25°C
900
Crss
600
Ciss
300
0
10
505
VGS VDS
Coss
Crss
10 15 20 25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
http://onsemi.com
5
5 Page 
MTB15N06V
PACKAGE DIMENSIONS
CASE 418B−02
ISSUE B
C
E
BV
4
123
S
A
−T−
SEATING
PLANE
G
K
J
D 3 PL
0.13 (0.005) M T
H
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES
DIM MIN MAX
A 0.340 0.380
B 0.380 0.405
C 0.160 0.190
D 0.020 0.035
E 0.045 0.055
G 0.100 BSC
H 0.080 0.110
J 0.018 0.025
K 0.090 0.110
S 0.575 0.625
V 0.045 0.055
MILLIMETERS
MIN MAX
8.64 9.65
9.65 10.29
4.06 4.83
0.51 0.89
1.14 1.40
2.54 BSC
2.03 2.79
0.46 0.64
2.29 2.79
14.60 15.88
1.14 1.40
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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11
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MTB15N06V/D
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet MTB15N06V.PDF ] | |
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