NP34N055ILE 반도체 회로 부품 판매점
MOS FIELD EFFECT TRANSISTOR
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 Renesas |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP34N055HLE, NP34N055ILE, NP34N055SLE
SWITCHING
N-CHANNEL POWER MOSFET
DESCRIPTION
These products are N-Channel MOS Field Effect Tran-
sistors designed for high current switching applications.
ORDERING INFORMATION
PART NUMBER
PACKAGE
NP34N055HLE
TO-251 (JEITA) / MP-3
FEATURES
• Channel temperature 175 degree rated
• Super low on-state resistance
RDS(on)1 = 18 mΩ MAX. (VGS = 10 V, ID = 17 A)
RDS(on)2 = 22 mΩ MAX. (VGS = 5 V, ID = 17 A)
• Low Ciss : Ciss = 2000 pF TYP.
• Built-in gate protection diode
NP34N055ILE Note
NP34N055SLE
Note Not for new design.
TO-252 (JEITA) / MP-3Z
TO-252 (JEDEC) / MP-3ZK
(TO-251)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage
VDSS
55 V
Gate to Source Voltage
VGSS
±20 V
Drain Current (DC)
Drain Current (Pulse) Note1
Total Power Dissipation (TA = 25°C)
ID(DC)
ID(pulse)
PT
±34
±136
1.2
A
A
W
(TO-252)
Total Power Dissipation (TC = 25°C)
Single Avalanche Current Note2
Single Avalanche Energy Note2
PT 88 W
IAS 34 / 27 / 10 A
EAS 11 / 72 / 100 mJ
Channel Temperature
Tch 175 °C
Storage Temperature
Tstg –55 to + 175 °C
Notes 1. PW ≤ 10 µ s, Duty Cycle ≤ 1%
2. Starting Tch = 25°C, RG = 25 Ω, VGS = 20 → 0 V (See Figure 4.)
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
1.70 °C/W
125 °C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D14154EJ4V0DS00 (4th edition)
Date Published July 2005 NS CP(K)
Printed in Japan
The mark shows major revised points.
1999, 2005
NP34N055HLE, NP34N055ILE, NP34N055SLE
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)1
RDS(on)2
RDS(on)3
Ciss
Coss
Crss
td(on)
tr
td(off)
VDS = 55 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 µA
VDS = 10 V, ID = 17 A
VGS = 10 V, ID = 17 A
VGS = 5 V, ID = 17 A
VGS = 4.5 V, ID = 17 A
VDS = 25 V
VGS = 0 V
f = 1 MHz
VDD = 28 V, ID = 17 A
VGS = 10 V
RG = 1 Ω
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage Note
Reverse Recovery Time
Reverse Recovery Charge
Note Pulsed
tf
QG1
QG2
QGS
QGD
VF(S-D)
trr
Qrr
VDD = 44 V, VGS = 10 V, ID = 34 A
VDD = 44 V
VGS = 5 V
ID = 34 A
IF = 34 A, VGS = 0 V
IF = 34 A, VGS = 0 V
di/dt = 100 A/µs
MIN.
1.5
9
TYP.
2
19
14
17
18
2000
250
130
17
11
57
9
41
23
7
12
1.0
42
58
MAX.
10
±10
2.5
18
22
24
3000
380
230
37
28
110
23
72
35
UNIT
µA
µA
V
S
mΩ
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
PG.
VGS = 20 → 0 V
50 Ω
L
VDD
BVDSS
ID
VDD
IAS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 µs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
Wave Form
0
td(on)
VGS 90%
90%
10% 10%
tr td(off) tf
ton toff
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
2 Data Sheet D14154EJ4V0DS
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