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NEC |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP15P04SLG
SWITCHING
P-CHANNEL POWER MOSFET
DESCRIPTION
The NP15P04SLG is P-channel MOS Field Effect Transistor designed for high current switching applications.
ORDERING INFORMATION
PART NUMBER
NP15P04SLG-E1-AY Note
NP15P04SLG-E2-AY Note
LEAD PLATING
Pure Sn (Tin)
PACKING
Tape 2500 p/reel
Note Pb-free (This product does not contain Pb in external electrode.)
PACKAGE
TO-252 (MP-3ZK)
FEATURES
• Super low on-state resistance
RDS(on)1 = 40 mΩ MAX. (VGS = −10 V, ID = −7.5 A)
RDS(on)2 = 60 mΩ MAX. (VGS = −4.5 V, ID = −7.5 A)
• Low input capacitance
Ciss = 1100 pF TYP.
• Built-in gate protection diode
(TO-252)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
Gate to Source Voltage (VDS = 0 V)
VGSS
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
ID(DC)
ID(pulse)
Total Power Dissipation (TC = 25°C)
PT1
Total Power Dissipation (TA = 25°C)
PT2
Channel Temperature
Tch
Storage Temperature
Single Avalanche Current Note2
Single Avalanche Energy Note2
Tstg
IAS
EAS
−40
m20
m15
m45
30
1.2
175
−55 to +175
16
25
Notes 1. PW ≤ 10 μs, Duty Cycle ≤ 1%
<R> 2. Starting Tch = 25°C, VDD = −20 V, RG = 25 Ω, VGS = −20 → 0 V
V
V
A
A
W
W
°C
°C
A
mJ
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
5.0
125
°C/W
°C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D19077EJ2V0DS00 (2nd edition)
Date Published March 2008 NS
Printed in Japan
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
2007
NP15P04SLG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS VDS = −40 V, VGS = 0 V
Gate Leakage Current
IGSS
Gate to Source Threshold Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
VGS(th)
| yfs |
RDS(on)1
VGS = m20 V, VDS = 0 V
VDS = VGS, ID = −250 μA
VDS = −10 V, ID = −7.5 A
VGS = −10 V, ID = −7.5 A
RDS(on)2
VGS = −4.5 V, ID = −7.5 A
Input Capacitance
Ciss VDS = −10 V,
Output Capacitance
Coss
VGS = 0 V,
Reverse Transfer Capacitance
Crss f = 1 MHz
Turn-on Delay Time
Td(on)
VDD = −20 V, ID = −7.5 A,
Rise Time
Tr VGS = −10 V,
Turn-off Delay Time
Td(off)
RG = 0 Ω
Fall Time
Tf
Total Gate Charge
QG VDD = −32 V,
<R>
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage Note
QGS
QGD
VF(S-D)
VGS = −10 V,
ID = −15 A
IF = −15 A, VGS = 0 V
<R>
Reverse Recovery Time
Reverse Recovery Charge
trr IF = −15 A, VGS = 0 V,
Qrr di/dt = −100 A/μs
Note Pulsed test PW ≤ 350 μs, Duty Cycle ≤ 2%
MIN.
−1.0
6
TYP.
−1.6
12
31
38
1100
190
140
7
5
100
65
23
3
7
0.94
32
33
MAX.
−10
m10
−2.5
40
60
1.5
UNIT
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
VGS = −20 → 0 V
50 Ω
VDD
− IAS BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS(−)
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS(−)
VGS
Wave Form
0 10%
VDS(−)
90%
VDS
VDS
Wave Form 0
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = −2 mA
PG. 50 Ω
RL
VDD
2 Data Sheet D19077EJ2V0DS
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