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6N136M 반도체 회로 부품 판매점

Single-Channel High Speed Transistor Optocouplers



Fairchild Semiconductor 로고
Fairchild Semiconductor
6N136M 데이터시트, 핀배열, 회로
March 2014
Single-Channel: 6N135M, 6N136M, HCPL4503M
Dual-Channel: HCPL2530M, HCPL2531M
High Speed Transistor Optocouplers
Features
High Speed –1 MBit/s
Superior CMR – 10 kV/µs
Dual-Channel: HCPL2530M, HCPL2531M
CTR Guaranteed 0°C to 70°C
U.L. Recognized (File # E90700, Vol. 2)
DIN EN/IEC60747-5-5
– Ordering Option ‘V’, e.g., 6N135VM
5,000 VRMS (1 Minute) Isolation Rating
Superior CMR of 15,000 V/µs Minimum (HCPL4503M)
No Base Connection for Improved Noise Immunity
(HCPL4503M)
Applications
Line Receivers
Pulse Transformer Replacement
Output Interface to CMOS-LSTTL-TTL
Wide-Bandwidth Analog Coupling
Description
The HCPL4503M, 6N135M, 6N136M, HCPL2530M, and
HCPL2531M optocouplers consist of an AlGaAs LED
optically coupled to a high speed photodetector transistor.
A separate connection for the bias of the photodiode
improves the speed by several orders of magnitude over
conventional phototransistor optocouplers by reducing
the base-collector capacitance of the input transistor.
The HCPL4503M has no internal connection to the
phototransistor base for improved noise immunity.
An internal noise shield provides superior common
mode rejection of up to 50,000 V/µs.
Related Resources
www.fairchildsemi.com/products/opto/
www.fairchildsemi.com/pf/HC/HCPL0500.html
www.fairchildsemi.com/pf/FO/FODM452.html
www.fairchildsemi.com/pf/FO/FOD050L.html
Schematics
Package Outlines
N/C 1
+2
V
F
_3
N/C 4
8
V
CC
7V
B
+1
V
F1
_2
6V
O
5 GND
_3
V
F2
+4
8
V
CC
8
7
V
01
6
V
02
5 GND
8
11
8
1
8
1
Figure 2. Package Outlines
6N135M, 6N136M, HCPL4503M
HCPL2530M/HCPL2531M
Pin 7 is not connected in the
HCPL4503M
Figure 1. Schematics
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.12
www.fairchildsemi.com


6N136M 데이터시트, 핀배열, 회로
Safety and Insulation Ratings for 8-Pin DIP White
As per DIN EN/IEC 60747-5-5. This optocoupler is suitable for “safe electrical insulation” only within the safety limit
data. Compliance with the safety ratings shall be ensured by means of protective circuits.
Symbol
Parameter
Installation Classifications per DIN VDE 0110/1.89 Table 1
For Rated Mains Voltage < 150 VRMS
For Rated Mains Voltage < 300 VRMS
For Rated Mains Voltage < 450 VRMS
For Rated Mains Voltage < 600 VRMS
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
CTI Comparative Tracking Index
VPR
VIORM
VIOTM
Input to Output Test Voltage, Method b,
VIORM x 1.875 = VPR, 100% Production Test with
tm = 1 s, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a,
VIORM x 1.5 = VPR, Type and Sample Test with
tm = 60 s, Partial Discharge < 5 pC
Max Working Insulation Voltage
Highest Allowable Over Voltage
External Creepage
External Clearance
External Clearance (for Option T, 0.4” Lead Spacing)
Insulation Thickness
Safety Limit Values, Maximum Values Allowed in the
Event of a Failure
TS
IS,INPUT
PS,OUTPUT
RIO
Case Temperature
Input Current
Output Power (Duty Factor 2.7%)
Insulation Resistance at TS, VIO = 500 V
Min.
Typ. Max. Unit
175
1,669
I–IV
I–IV
I–III
I–III
40/100/21
2
1,335
890
6,000
8.0
7.4
10.16
0.5
VPEAK
VPEAK
mm
mm
mm
mm
150 °C
200 mA
300 mW
109 Ω
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.12
2
www.fairchildsemi.com




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