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PDF BLF6G10LS-135R Data sheet ( Hoja de datos )
| Número de pieza | BLF6G10LS-135R | |
| Descripción | Power LDMOS transistor | |
| Fabricantes | NXP Semiconductors | |
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BLF6G10LS-135R
Power LDMOS transistor
Rev. 01 — 17 November 2008
Product data sheet
1. Product profile
1.1 General description
135 W LDMOS power transistor for base station applications at frequencies from
800 MHz to 1000 MHz.
Table 1. Typical performance
Typical RF performance at Tcase = 25 °C in a class-AB production test circuit.
Mode of operation
f
VDS PL(AV)
Gp
ηD
(MHz)
(V) (W)
(dB) (%)
2-carrier W-CDMA
869 to 894
28 26.5
21.0 28.0
ACPR
(dBc)
−39[1]
[1] Test signal: 3GPP; test model 1; 64 DPCH; PAR = 7.5 dB at 0.01 % probability on CCDF per carrier;
carrier spacing 5 MHz.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
1.2 Features
I Typical 2-carrier W-CDMA performance at frequencies of 869 MHz and 894 MHz, a
supply voltage of 28 V and an IDq of 950 mA:
N Average output power = 26.5 W
N Power gain = 21.0 dB
N Efficiency = 28.0 %
N ACPR = −39 dBc
I Easy power control
I Integrated ESD protection
I Excellent ruggedness
I High efficiency
I Excellent thermal stability
I Designed for broadband operation (800 MHz to 1000 MHz)
I Internally matched for ease of use
I Compliant to Directive 2002/95/EC, regarding restriction of hazardous substances
(RoHS)
1 page  
www.DNatXaSPheSete4Um.coicmonductors
BLF6G10LS-135R
Power LDMOS transistor
24
Gp
(dB)
23
22
Gp
21
ηD
20
001aah867 50
ηD
(%)
40
30
20
10
−20
ACPR
(dBc)
−30
−40
001aah868
19
0
0
12 24 36 48 60
PL(AV) (W)
Fig 4.
VDS = 28 V; IDq = 950 mA; f1 = 881 MHz; f2 = 886 MHz;
carrier spacing 5 MHz.
2-carrier W-CDMA power gain and drain
efficiency as function of average load power;
typical values
−50
0
20 40 60
PL(AV) (W)
Fig 5.
VDS = 28 V; IDq = 950 mA; f1 = 881 MHz; f2 = 886 MHz;
carrier spacing 5 MHz.
2-carrier W-CDMA adjacent power channel
ratio as a function of average load power;
typical values
8. Test information
input
50 Ω
VGG
R1
C3
C4
R2
C1
C2
C5
C8 C9 C10 C11 C18
R3
L1
C6
C7
C12 C13 C14 C15 C19
The drawing is not to scale.
Fig 6. Test circuit for operation at 800 MHz
VDD
C20
C17
C16
output
50 Ω
001aah869
BLF6G10LS-135R_1
Product data sheet
Rev. 01 — 17 November 2008
© NXP B.V. 2008. All rights reserved.
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