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NP100P04PLG 반도체 회로 부품 판매점

MOS FIELD EFFECT TRANSISTOR



NEC 로고
NEC
NP100P04PLG 데이터시트, 핀배열, 회로
www.DataSheet4U.com
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP100P04PLG
SWITCHING
P-CHANNEL POWER MOSFET
DESCRIPTION
The NP100P04PLG is P-channel MOS Field Effect Transistor designed for high current switching applications.
<R>
ORDERING INFORMATION
PART NUMBER
NP100P04PLG-E1-AY Note
NP100P04PLG-E2-AY Note
LEAD PLATING
Pure Sn (Tin)
PACKING
Tape 800 p/reel
Note Pb-free (This product does not contain Pb in external electrode.)
PACKAGE
TO-263 (MP-25ZP)
FEATURES
Super low on-state resistance
RDS(on)1 = 3.7 mΩ MAX. (VGS = 10 V, ID = 50 A)
RDS(on)2 = 5.1 mΩ MAX. (VGS = 4.5 V, ID = 50 A)
High current rating: ID(DC) = m100 A
Built-in gate protection diode
(TO-263)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
Gate to Source Voltage (VDS = 0 V)
VGSS
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
ID(DC)
ID(pulse)
Total Power Dissipation (TC = 25°C)
PT1
Total Power Dissipation (TA = 25°C)
PT2
Channel Temperature
Tch
Storage Temperature
Single Avalanche Current Note2
Single Avalanche Energy Note2
Tstg
IAS
EAS
40
m20
m100
m300
200
1.8
175
55 to +175
74
550
Notes 1. PW 10 μs, Duty Cycle 1%
2. Starting Tch = 25°C, VDD = 30 V, RG = 25 Ω, VGS = 20 0 V
V
V
A
A
W
W
°C
°C
A
mJ
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
0.75
83.3
°C/W
°C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D18694EJ3V0DS00 (3rd edition)
Date Published May 2007 NS CP(K)
Printed in Japan
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
2007


NP100P04PLG 데이터시트, 핀배열, 회로
NP100P04PLG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS VDS = 40 V, VGS = 0 V
Gate Leakage Current
IGSS
Gate to Source Threshold Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
VGS(th)
| yfs |
RDS(on)1
VGS = m20 V, VDS = 0 V
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 50 A
VGS = 10 V, ID = 50 A
RDS(on)2
VGS = 4.5 V, ID = 50 A
Input Capacitance
Ciss VDS = 10 V,
Output Capacitance
Coss
VGS = 0 V,
Reverse Transfer Capacitance
Crss f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 20 V, ID = 50 A,
Rise Time
tr VGS = 10 V,
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
tf
Total Gate Charge
QG VDD = 32 V,
Gate to Source Charge
QGS VGS = 10 V,
Gate to Drain Charge
Body Diode Forward Voltage Note
QGD
VF(S-D)
ID = 100 A
IF = 100 A, VGS = 0 V
Reverse Recovery Time
trr IF = 100 A, VGS = 0 V,
Reverse Recovery Charge
Qrr di/dt = 100 A/μs
Note Pulsed test PW 350 μs, Duty Cycle 2%
MIN.
1.0
43
TYP.
1.6
88
2.8
3.4
15100
2400
1130
38
30
300
100
320
37
85
0.91
70
123
MAX.
10
m10
2.5
3.7
5.1
1.5
UNIT
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
VGS = 20 0 V
50 Ω
VDD
IAS BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS()
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS()
VGS
Wave Form
0 10%
VDS()
90%
VDS
VDS
Wave Form 0
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
2 Data Sheet D18694EJ3V0DS




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