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SPI100N03S2L-03 반도체 회로 부품 판매점

OptiMOS Power-Transistor



Infineon Technologies 로고
Infineon Technologies
SPI100N03S2L-03 데이터시트, 핀배열, 회로
SPI100N03S2L-03
SPP100N03S2L-03,SPB100N03S2L-03
OptiMOS® Power-Transistor
Feature
N-Channel
Enhancement mode
Logic Level
Excellent Gate Charge x RDS(on)
product (FOM)
Superior thermal resistance
175°C operating temperature
Avalanche rated
dv/dt rated
P- TO262 -3-1
Product Summary
VDS 30 V
RDS(on) max. SMD version 2.7 m
ID 100 A
P- TO263 -3-2
P- TO220 -3-1
Type
Package
Ordering Code
SPP100N03S2L-03 P- TO220 -3-1 Q67042-S4056
SPB100N03S2L-03 P- TO263 -3-2 Q67042-S4055
SPI100N03S2L-03 P- TO262 -3-1 Q67042-S4094
Marking
PN03L03
PN03L03
PN03L03
Maximum Ratings, at Tj = 25 °C, unless otherwise specified
Parameter
Symbol
Continuous drain current 1)
TC=25°C
ID
Pulsed drain current
TC=25°C
Avalanche energy, single pulse
ID=80 , VDD=25V, RGS=25
Repetitive avalanche energy, limited by Tjmax2)
Reverse diode dv/dt
IS=100A, VDS=24V, di/dt=200A/µs, Tjmax=175°C
Gate source voltage
Power dissipation
TC=25°C
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
ID puls
EAS
EAR
dv/dt
VGS
Ptot
Tj , Tstg
Value
100
100
400
810
30
6
±20
300
-55... +175
55/175/56
Unit
A
mJ
kV/µs
V
W
°C
Page 1
2003-05-09


SPI100N03S2L-03 데이터시트, 핀배열, 회로
Thermal Characteristics
Parameter
Characteristics
Thermal resistance, junction - case
Thermal resistance, junction - ambient, leaded
SMD version, device on PCB:
@ min. footprint
@ 6 cm2 cooling area 3)
SPI100N03S2L-03
SPP100N03S2L-03,SPB100N03S2L-03
Symbol
Values
Unit
min. typ. max.
RthJC
RthJA
RthJA
- 0.3 0.5 K/W
- - 62
- - 62
- - 40
Electrical Characteristics, at Tj = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Unit
min. typ. max.
Static Characteristics
Drain-source breakdown voltage
VGS=0V, ID=1mA
Gate threshold voltage, VGS = VDS
ID = 250 µA
Zero gate voltage drain current
VDS=30V, VGS=0V, Tj=25°C
VDS=30V, VGS=0V, Tj=125°C
Gate-source leakage current
VGS=20V, VDS=0V
Drain-source on-state resistance
VGS=4.5V, ID=80A
VGS=4.5V, ID=80A, SMD version
V(BR)DSS 30
-
-V
VGS(th) 1.2 1.6
2
IDSS
IGSS
µA
- 0.01 1
- 1 100
- 1 100 nA
RDS(on)
m
- 2.8 3.7
- 2.5 3.4
Drain-source on-state resistance
VGS=10V, ID=80A
VGS=10V, ID=80A, SMD version
RDS(on)
- 2.2 3
- 1.9 2.7
1Current limited by bondwire ; with an RthJC = 0.5K/W the chip is able to carry ID= 245A at 25°C, for detailed
information see app.-note ANPS071E available at www.infineon.com/optimos
2Defined by design. Not subject to production test.
3Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical without blown air.
Page 2
2003-05-09




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SPI100N03S2L-03 transistor

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SPI100N03S2L-03

OptiMOS Power-Transistor - Infineon Technologies



SPI100N03S2L-03

OptiMOS Power-Transistor - Infineon Technologies