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PDF UPA104 Data sheet ( Hoja de datos )
| Número de pieza | UPA104 | |
| Descripción | HIGH FREQUENCY NPN TRANSISTOR ARRAY | |
| Fabricantes | NEC | |
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DATA SHEET
COMPOUND TRANSISTOR
µPA104
HIGH FREQUENCY NPN TRANSISTOR ARRAY
FEATURES
• 9 GHz CONFIGURABLE TRANSISTOR BASED OR/NOR CIRCUITRY
• OUTSTANDING hFE LINEARITY
• TWO PACKAGE OPTIONS:
µPA104B: Studded ceramic package provides superior thermal dissipation
µPA104G: Reduced circuit size due to 14-pin plastic SOP package for surface mounting
• EXCELLENT FOR ANALOG ADDITIONS & FORMATION OF 2-INPUT OR/NOR GATES
DESCRIPTION AND APPLICATIONS
The µPA104 is a user-configurable, Si bipolar transistor array for formation of high speed OR/NOR gates. Its
internal transistor configuration and external connection options allow the user considerable flexibility in its
application. Its high gain bandwidth product (fT = 9 GHz) make it applicable for electro-optical, signal processing,
cellular telephone systems, instrumentation, and high speed gigabit logic circuits.
ORDERING INFORMATION
PART NUMBER
PACKAGE
µPA104B-E1
14-pin ceramic package
µPA104G-E1
14-pin plastic SOP (225 mil)
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
SYMBOLS
PARAMETERS
UNITS RATINGS
VCBO*
Collector to Base Voltage V
15
VCEO*
Collector to Emitter Voltage
V
6
VEBO*
Emitter to Base Voltage
V
2.5
IC* Collector Current
mA 40
PT Power Dissipation
µPA104B mW
µPA104G mW
650
350
TJ Junction Temperature
µPA104B °C
µPA104G °C
200
125
TSTG
Storage Temperature
µPA104B °C –55 to +200
µPA104G °C –55 to +125
* Absolute maximum ratings for each transistor.
Caution electro-static sensitive devices
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. P10709EJ2V0DS00 (2nd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1995, 1999
1 page  
TYPICAL APPLICATION
A
B
A+B
AB
100 Ω 115 Ω
OR
300 Ω
VCC (+2 V)
µPA104
OR
50 Ω
50 KΩ
100 Ω
50 KΩ 47 Ω 1.5 KΩ
VBB (–1.6 V)
2.8 KΩ
VEE (–3.2 V)
IN
OUT (OR)
50 %
t++
50 %
t––
50 %
50 %
tf
90 %
10 %
tR
tf = 500 psec. t++ = 500 psec.
tR = 750 psec. t–– = 250 psec.
+1.1 V
+0.3 V
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
Data Sheet P10709EJ2V0DS00
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet UPA104.PDF ] | |
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