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FDC634P 반도체 회로 부품 판매점

P-Channel Enhancement Mode Field Effect Transistor



Fairchild Semiconductor 로고
Fairchild Semiconductor
FDC634P 데이터시트, 핀배열, 회로
November 1997
FDC634P
P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited
for low voltage applications such as cellular phone and
notebook computer power management and other battery
powered circuits where high-side switching, and low in-line
power loss are needed in a very small outline surface
mount package.
Features
-3.5 A, -20 V. RDS(ON) = 0.080 @ VGS = -4.5 V
RDS(ON) = 0.110 @ VGS = -2.5 V.
SuperSOTTM-6 package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
S
D
D .634
G
D
SuperSOT TM -6 pin 1 D
Absolute Maximum RatingsTA = 25°C unless otherwise note
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain Current - Continuous
- Pulsed
(Note 1a)
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient
RθJC Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
© 1997 Fairchild Semiconductor Corporation
16
25
34
FDC634P
-20
±8
-3.5
-11
1.6
0.8
-55 to 150
78
30
Units
V
V
A
W
°C
°C/W
°C/W
FDC634P Rev.C


FDC634P 데이터시트, 핀배열, 회로
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol Parameter
Conditions
Min Typ Max Units
OFF CHARACTERISTICS
BVDSS
BVDSS/TJ
IDSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
IGSSF Gate - Body Leakage, Forward
IGSSR Gate - Body Leakage, Reverse
ON CHARACTERISTICS (Note 2)
VGS = 0 V, ID = -250 µA
ID = -250 µA, Referenced to 25 o C
VDS = -16 V, VGS = 0 V
VGS = 8 V, VDS = 0 V
TJ = 55oC
VGS = -8 V, VDS= 0 V
-20
-29
V
mV /oC
-1 µA
-10 µA
100 nA
-100 nA
VGS(th)
VGS(th)/TJ
RDS(ON)
Gate Threshold Voltage
Gate Threshold VoltageTemp.Coefficient
Static Drain-Source On-Resistance
ID(on) On-State Drain Current
gFS Forward Transconductance
DYNAMIC CHARACTERISTICS
VDS = VGS, ID = -250 µA
ID = -250 µA, Referenced to 25 o C
VGS = -4.5 V, ID = -3.5 A
TJ = 125oC
VGS = -2.5 V, ID= -3.1 A
VGS = -4.5 V, VDS = -5 V
VDS = -10 V, ID= -3.5 A
-0.4 -0.6
2.1
0.07
0.099
0.093
-10
6.5
-1 V
mV /oC
0.08
0.13
0.11
A
S
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
665 pF
270 pF
70 pF
tD(on) Turn - On Delay Time
tr Turn - On Rise Time
tD(off) Turn - Off Delay Time
tf Turn - Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
DRAIN-SOURCE DIODE CHARACTERISTICS
VDD = -5 V, ID = -1 A,
VGS = -4.5 V, RGEN = 6
VDS = -5 V, ID = -3.5 A,
VGS = -4.5 V
8 16 ns
24 38 ns
50 80 ns
29 45 ns
9.5 13 nC
1.3 nC
2.2 nC
IS Continuous Source Diode Current
-1.3 A
VSD Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -1.3 A (Note 2)
-0.75 -1.2
V
TJ = 125oC
-0.6 -1
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
a. 78oC/W when mounted on a 1 in2 pad of 2oz Cu in FR-4 board.
b. 156oC/W when mounted on a minimum pad of 2oz Cu in FR-4 board.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDC634P Rev.C




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FDC634P transistor

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FDC634

P-Channel Enhancement Mode Field Effect Transistor - Fairchild Semiconductor



FDC634P

P-Channel Enhancement Mode Field Effect Transistor - Fairchild Semiconductor