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PDF 74AVCH8T245 Data sheet ( Hoja de datos )
| Número de pieza | 74AVCH8T245 | |
| Descripción | 8-bit dual supply translating transceiver | |
| Fabricantes | NXP Semiconductors | |
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74AVCH8T245
8-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 5 — 27 December 2012
Product data sheet
1. General description
The 74AVCH8T245 is an 8-bit, dual supply transceiver that enables bidirectional level
translation. It features two 8-bit input-output ports (An and Bn), a direction control input
(DIR), a output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A)
and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device
suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V and 3.3 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are
referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on
DIR allows transmission from Bn to An. The output enable input (OE) can be used to
disable the outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both An and Bn outputs are in the high-impedance OFF-state. The bus-hold
circuitry on the powered-up side always stays active.
The 74AVCH8T245 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features and benefits
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
380 Mbit/s ( 1.8 V to 3.3 V translation)
260 Mbit/s ( 1.1 V to 3.3 V translation)
1 page  
NXP Semiconductors
74AVCH8T245
8-bit dual supply translating transceiver; 3-state
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
IGND
Tstg
Ptot
ground current
storage temperature
total power dissipation
per GND pin
Tamb = 40 C to +125 C
100
65
[4] -
-
+150
500
mA
C
mW
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 4.6 V.
[4] For TSSOP24 package: Ptot derates linearly at 5.5 mW/K above 60 C.
For DHVQFN24 package: Ptot derates linearly at 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Symbol
VCC(A)
VCC(B)
VI
VO
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage A
supply voltage B
input voltage
output voltage
Active mode
Suspend or 3-state mode
ambient temperature
input transition rise and fall rate VCCI = 0.8 V to 3.6 V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
9. Static characteristics
Min
0.8
0.8
0
[1] 0
0
40
[2] -
Max
3.6
3.6
3.6
VCCO
3.6
+125
5
Unit
V
V
V
V
V
C
ns/V
Table 6. Typical static characteristics at Tamb = 25 C[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VOH
VOL
II
IBHL
IBHH
IBHLO
HIGH-level output voltage
LOW-level output voltage
input leakage current
bus hold LOW current
bus hold HIGH current
bus hold LOW overdrive
current
VI = VIH or VIL
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
VI = VIH or VIL
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
DIR, OE input; VI = 0 V or 3.6 V;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
A or B port; VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V
A or B port; VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V
A or B port; VCC(A) = VCC(B) = 1.2 V
IBHHO
bus hold HIGH overdrive A or B port; VCC(A) = VCC(B) = 1.2 V
current
Min
-
-
-
[3] -
[4] -
[5] -
[6] -
Typ Max Unit
0.69 -
V
0.07 -
V
0.025 0.25 A
26 -
24 -
27 -
A
A
A
26 -
A
74AVCH8T245
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 December 2012
© NXP B.V. 2012. All rights reserved.
5 of 25
5 Page 
NXP Semiconductors
74AVCH8T245
8-bit dual supply translating transceiver; 3-state
Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
0.8 V
1.2 V
VCC(A) = VCC(B)
1.5 V 1.8 V
CPD power dissipation A port: (direction An to 0.2 0.2 0.2 0.3
capacitance
Bn); output enabled
A port: (direction An to
0.2
0.2
0.2
0.3
Bn); output disabled
A port: (direction Bn to
An); output enabled
9
9 10 10
A port: (direction Bn to
0.6
0.6
0.6
0.7
An); output disabled
B port: (direction An to
Bn); output enabled
9
9 10 10
B port: (direction An to
0.6
0.6
0.6
0.7
Bn); output disabled
B port: (direction Bn to
0.2
0.2
0.2
0.3
An); output enabled
B port: (direction Bn to
0.2
0.2
0.2
0.3
An); output disabled
[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = .
2.5 V
0.4
0.4
11
0.7
11
0.7
0.4
0.4
3.3 V
0.5
Unit
pF
0.5 pF
13 pF
0.8 pF
13 pF
0.8 pF
0.5 pF
0.5 pF
74AVCH8T245
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 December 2012
© NXP B.V. 2012. All rights reserved.
11 of 25
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| Páginas | Total 25 Páginas | |
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