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PDF 78Q2120C Data sheet ( Hoja de datos )
| Número de pieza | 78Q2120C | |
| Descripción | 10/100BASE-TX Transceiver | |
| Fabricantes | Teridian | |
| Logotipo |  |
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78Q2120C
10/100BASE-TX
Transceiver
DATA SHEET
DESCRIPTION
The 78Q2120C is a 10BASE-T/100BASE-TX Fast
Ethernet transceiver. It includes integrated MII,
ENDECs, scrambler/descrambler, dual-speed clock
recovery, and full-featured auto-negotiation function.
The transmitter includes an on-chip pulse-shaper and
a low-power line driver. The receiver has an adaptive
equalizer and a baseline restoration circuit required
for accurate clock and data recovery. The transceiver
interfaces to Category-5 unshielded twisted pair (Cat-
5 UTP) cabling for 100BASE-TX/10BASE-T and
Category-3 unshielded twisted pair for 10BASE-T.
Connection to the line media is via 1:1 isolation
transformers. No external filter is required. Interface
to the MAC is accomplished through an IEEE-802.3
compliant Media Independent Interface (MII). The
product is fabricated in an advanced CMOS process
for high performance and low power operation.
FEATURES
JULY 2005
• 10BASE-T/100BASE-TX IEEE-802.3 compliant
TX and RX functions requiring a dual 1:1
isolation transformer interface to the line
• Integrated MII, 10BASE-T/100BASE-TX ENDEC,
100BASE-TX scrambler/descrambler, and full-
featured auto-negotiation function
• Full duplex operation capable
• PCS Bypass supports 5-bit symbol interface
• Register-programmable transmit amplitude
• Dual speed digital clock recovery
• Automatic polarity correction during auto-
negotiation and 10BASE-T signal reception
• Power-saving and power-down modes
including transmitter disable
• LED indicators: LINK, TX, RX, COL, 100, 10,
FDX
• User programmable Interrupt pin
• 64-Pin TQFP (JEDEC LQFP) package
• Single 3.3 V ± 0.3V Supply
BLOCK DIAGRAM
RX_CLK
TX_CLK
RXD[3:0]
TXD[3:0]
4B/5B Encoder,
100M Scrambler,
Parallel/Serial
NRZ/NRZI
MLT3 Encoder
MII
Registers
&
Interface
Logic
10M Parallel/Serial,
MMaanncchheesstteerr EEnnccooddeerr
TX CLK GEN
Manchester Decoder,
Parallel/Serial
Carrier Sense,
CCoollliissiioonn DDeetteecctt
CLK
Recovery
Serial/Parallel
Descrambler,
5B/4B Decoder
CClloocckk RReeffeerreennccee
PS
PPuullssee SShhaappeerr
and Filter
Auto
Negotiation
TXOP/N
MDI
RXIP/N
10M 100M
Adaptive EQ,
Baseline Wander Correct,
MMLLTT33 DDeeccooddee,, NNRRZZII//NNRRZZ
LEDs
VCC GND
LEDL LEDBTX LEDTX LEDCOL
CKIN 25MHz
LEDBT LEDFX
LEDRX
Page: 1 of 34
© 2005 Teridian Semiconductor Corporation
Rev 1.2
1 page  
The receive clock, RX_CLK, provides the timing
reference to transfer RX_DV, RXD[3:0], and RX_ER
signals from the 78Q2120C to the MAC. RX_DV
transitions synchronously with respect to RX_CLK
and is asserted when the 78Q2120C is presenting
valid data on RXD[3:0]. RX_ER is asserted and is
synchronous to RX_CLK when a code group
violation has been detected in the current receive
packet.
Station Management Interface
The station management interface consists of
circuitry which implements the serial protocol as
described in Clause 22.2.4.5 of IEEE-802.3. A 16-
bit shift register receives serial data applied to the
MDIO pin at the rising-edge of the MDC clock signal.
Once the preamble is received, the station
management control logic looks for the start-of-
frame sequence and a read or write op-code,
followed by the PHYAD and REGAD fields. For a
read operation, the MDIO port becomes enabled as
an output and the register data is loaded into a shift
register for transmission. The 78Q2120C can work
with a one bit preamble rather than the 32 bits
prescribed by IEEE-802.3. This allows for faster
programming of the registers. If a register does not
exist at an address indicated by the REGAD field or
if the PHYAD field does not match the 78Q2120C
PHYAD indicated by the PHYAD pins, a read of the
MDIO port will return all ones. For a write operation,
the data is shifted in and loaded into the appropriate
register after the sixteenth data bit has been
received.
When the PHYAD field is all zeros, the Station
Management Entity (STA) is requesting a broadcast
data transaction. All PHYs sharing the same
Management Interface must respond to this
broadcast request. The 78Q2120C will respond to
the broadcast data transaction.
78Q2120C
10/100BASE-TX
Transceiver
ADDITIONAL FEATURES
LED Indicators
There are seven LED pins that can be used to
indicate various states of operation of the
78Q2120C. There is an LED pin that indicates the
link is up (LEDL), others that indicate the 78Q2120C
is either transmitting (LEDTX) or receiving (LEDRX),
one that signals a collision event (LEDCOL), two
more that reflect the data rate (LEDBTX and
LEDBT), and one that reflects full duplex mode of
operation (LEDFDX).
Interrupt Pin
The 78Q2120C has an Interrupt pin (INTR) that is
asserted whenever any of the eight interrupt bits of
MR17.7:0 are set. These interrupt bits can be
disabled via the MR17.15:8 Interrupt Enable bits.
The Interrupt Polarity bit, MR16.14, controls the
active level of the INTR pin. When the INTR pin is
not asserted, this pin is held in a high impedance
state. An external pull-up or pull-down resistor may
be required for use with the INTR pin.
APPLICATIONS REQUIREMENTS
RXIP/N Termination Connection
The input circuitry of the TERIDIAN 78Q2120C has
changed for continuing performance improvements.
Device revision C09 requires that the RXIP/N
termination resistors and transformer center tap
connections be directly connected to VCC for proper
receiver operation. Refer to Figure 1: Typical
Applications Circuit for the schematic showing the
required RXIP/N termination resistors and
transformer center tap connections to VCC for
revision 78Q2120C.
Page: 5 of 34
© 2005 Teridian Semiconductor Corporation
Rev 1.2
5 Page 
78Q2120C
10/100BASE-TX
Transceiver
MR0: Control Register
BIT
0.15
0.14
0.13
0.12
0.11
0.10
0.9
SYMBOL TYPE
RESET R/SC
LOOPBK R/W
SPEEDSL R/W
ANEGEN R/W
PWRDN R/W
ISO R/W
RANEG R/SC
DEFAULT
0
0
(1)
(1)
0
(0)
0
DESCRIPTION
Reset: Setting this bit to ‘1’ resets the device and sets all registers
to their default states. This bit is self-clearing.
Loopback: When this bit is set to ‘1’, no transmission of data on the
network medium occurs and any receive data on the network
medium is ignored. The loopback signal path will encompass most
of the digital circuitry.
Speed Selection: This bit determines the speed of operation of the
78Q2120C. Setting this bit to ‘1’ indicates 100Base-TX operation
and a ‘0’ indicates 10Base-T mode. This bit will default to a ‘1’ upon
reset. If the TECH[2:0] pins are all logic zero and auto-negotiation is
not enabled, this bit will be writeable. If auto-negotiation is not
enabled and the TECH[2:0] pins are set to indicate that only
10Base-T is supported, this bit will be forced to logic zero and will
not be writeable. If auto-negotiation is not enabled and the
TECH[2:0] pins are set to indicate that only 100Base-TX is
supported, this bit will be forced to logic one and will not be
writeable. When auto-negotiation is enabled, this bit will not be
writeable and will have no effect on the 78Q2120C. If the
TECH[2:0] pins are brought to zero from another value, this bit will
retain its original value until it is overwritten.
Auto-Negotiation Enable: Setting this bit to ‘1’ enables the auto-
negotiation process. This bit can only be set if the ANEGA pin is a
logic one and will default to ‘1’ upon reset. If this bit is cleared to ‘0’,
manual speed and duplex mode selection is accomplished through
bits 0.13 (SPEEDSL) and 0.8 (DUPLEX) of the Control Register or
the TECH[2:0] pins according to the table shown in the section
describing the TECH[2:0] pins. If the ANEGA pin is brought from ‘0’
to ‘1’ and reset is not asserted, this bit will remain at ‘0’ until a ‘1’ is
written.
Power-Down: The device may be placed in a low power
consumption state by setting this bit to ‘1’. While in the power-down
state, the device will still respond to management transactions.
Setting the PWRDN pin high also activates the power-down state.
Isolate: When set to ‘1’, the device presents a high-impedance on
its MII output pins. This allows for multiple PHY’s to be attached to
the same MII interface. When the device is isolated, it still responds
to management transactions. The default value of this bit depends
on the ISODEF pin. When ISODEF pin is tied high, the ISO bit
defaults to high. Otherwise, it defaults to low. The Isolate mode can
also be activated using the ISO pin.
Restart Auto-Negotiation: Normally, the Auto-Negotiation process is
started at power up. The process can be restarted by setting this bit
to ‘1’. This bit is self-clearing.
Page: 11 of 34
© 2005 Teridian Semiconductor Corporation
Rev 1.2
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 78Q2120C.PDF ] | |
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