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74643 반도체 회로 부품 판매점

True-Inverting Octal TRI-STATE Transceiver



National Semiconductor 로고
National Semiconductor
74643 데이터시트, 핀배열, 회로
February 1988
MM54HCT640 MM74HCT640
Inverting Octal TRI-STATE Transceiver
MM54HCT643 MM74HCT643
True-Inverting Octal TRI-STATE Transceiver
General Description
These TRI-STATE bi-directional transceivers utilize advanced
silicon-gate CMOS technology and are intended for two-way
asynchronous communication between data buses They
have high drive current outputs which enable high speed
operation even when driving large bus capacitances These
circuits possess the low power consumption of CMOS cir-
cuitry yet have speeds comparable to low power Schottky
TTL circuits
All devices are TTL input compatible and can drive up to 15
LS-TTL loads and all inputs are protected from damage due
to static discharge by diodes to VCC and ground
Both the MM54HCT640 MM74HCT640 and the
MM54HCT643 MM74HCT643 have one active low enable
input (G) and a direction control (DIR) When the DIR input
is high data flows from the A inputs to the B outputs When
DIR is low data flows from B to A The MM54HCT640
MM74HCT640 transfers inverted data from one bus to the
other The MM54HCT643 MM74HCT643 transfers inverted
data from the A bus to the B bus and non-inverted data from
the B bus to the A bus
MM54HCT MM74HCT devices are intended to interface be-
tween TTL and NMOS components and standard CMOS
devices These parts are also plug-in replacements for LS-
TTL devices and can be used to reduce power consumption
in existing designs
Features
Y TTL input compatible
Y Octal TRI-STATE outputs for mP bus applications
6 mA typical
Y High speed 16 ns typical propagation delay
Y Low power 80 mA maximum (74HCT)
Connection Diagram
Dual-In-Line Packages
TL F 5370 – 1
Top View
Order Number MM54HCT640 or MM74HCT640
TL F 5370 – 2
Top View
Order Number MM54HCT643 or MM74HCT643
Truth Table
Control
Inputs
Operation
G DIR
640
643
L L B data to A bus B data to A bus
L H A data to B bus A data to B bus
HX
Isolation
Isolation
Hehigh level Lelow level Xeirrelevant
TRI-STATE is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL F 5370
RRD-B30M105 Printed in U S A


74643 데이터시트, 핀배열, 회로
Absolute Maximum Ratings (Notes 1 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK IOK)
DC Output Current per pin (IOUT)
DC VCC or GND Current per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S O Package only
b0 5 to a7 0V
b1 5 to VCCa1 5V
b0 5 to VCCa0 5V
g20 mA
g35 mA
g70 mA
b65 C to a150 C
600 mW
500 mW
Lead Temperature (TL)
(Soldering 10 seconds)
260 C
Operating Conditions
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN VOUT)
Operating Temp Range (TA)
MM74HCT
MM54HCT
Min
45
0
b40
b55
Input Rise or Fall Times
(tr tf)
Max
55
VCC
a85
a125
500
Units
V
V
C
C
ns
DC Electrical Characteristics VCCe5V g10% (unless otherwise specified)
Symbol
Parameter
Conditions
TAe25 C
74HCT
54HCT
TAeb40 to 85 C TAeb55 to 125 C
Typ Guaranteed Limits
Units
VIH Minimum High Level
Input Voltage
20 20
20 V
VIL Maximum Low Level
Input Voltage
08 08
08 V
VOH
Minimum High Level VINeVIH or VIL
Output Voltage
lIOUTle20 mA
VCC VCC-0 1
l lIOUT e6 0mA VCCe4 5V 4 2 3 98
l lIOUT e7 2mA VCCe5 5V 5 2 4 98
VOL Maximum Low Level VINeVIH or VIL
Voltage
lIOUTle20 mA
0 01
l lIOUT e6 0mA VCCe4 5V 0 2 0 26
l lIOUT e7 2mA VCCe5 5V 0 2 0 26
IIN Maximum Input
Current
VINeVCC or GND
VIH or VIL
g0 1
IOZ Maximum TRI-STATE VOUTeVCC or GND
Output Leakage
Enable GeVIH
Current
g0 5
VCC-0 1
3 84
4 84
01
0 33
0 33
g1 0
g5 0
VCC-0 1
37
47
01
04
04
g1 0
g10
V
V
V
V
V
V
mA
mA
ICC Maximum Quiescent VINeVCC or GND
Supply Current
IOUTe0mA
8 80
160 mA
VINe2 4V or 0 5V
(Note 4)
06 10
13
1 5 mA
Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur
Note 2 Unless otherwise specified all voltages are referenced to ground
Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b12 mW C from 100 C to 125 C
Note 4 Measured per input All other inputs held at VCC or ground
AC Electrical Characteristics MM54HCT640 MM74HCT640
VCCe5 0V tretfe6 ns TAe25 C (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limits
Units
tPHL tPLH
Maximum Output
Propagation Delay
CLe45 pF
16
20
ns
tPZL tPZH
tPLZ tPHZ
Maximum Output
Enable Time
Maximum Output
Disable Time
CLe45 pF
RLe1 kX
CLe5 pF
RLe1 kX
29
20
40
25
ns
ns
2




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74643 transceiver

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