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74AVC4T245
4-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 01 — 20 July 2009
Product data sheet
1. General description
The 74AVC4T245 is an 4-bit, dual supply transceiver that enables bidirectional level
translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It
features two data input-output ports (nAn and nBn), a direction control input (nDIR), a
output enable input (nOE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and
VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable
for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and
3.3 V). Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to
VCC(B). A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows
transmission from nBn to nAn. The output enable input (nOE) can be used to disable the
outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both nAn and nBn are in the high-impedance OFF-state.
2. Features
I Wide supply voltage range:
N VCC(A): 0.8 V to 3.6 V
N VCC(B): 0.8 V to 3.6 V
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3B exceeds 8000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Maximum data rates:
N 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
N 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
N 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
N 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
N 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
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NXP Semiconductors
74AVC4T245
4-bit dual supply translating transceiver; 3-state
N 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
I Suspend mode
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74AVC4T245D −40 °C to +125 °C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
74AVC4T245PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
74AVC4T245BQ −40 °C to +125 °C
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
Version
SOT109-1
SOT403-1
SOT763-1
4. Functional diagram
VCC(A)
13
VCC(B)
1B1
12
1B2
11
2B1
10
2B2
15 1OE
2 1DIR
Fig 1. Logic symbol
1A1
4
1A2
5
2A1
6
2A2
7
2OE 14
2DIR 3
001aak280
74AVC4T245_1
Product data sheet
Rev. 01 — 20 July 2009
© NXP B.V. 2009. All rights reserved.
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