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PDF ADF7023-J Data sheet ( Hoja de datos )
| Número de pieza | ADF7023-J | |
| Descripción | ISM Band FSK/GFSK/MSK/GMSK Transceiver IC | |
| Fabricantes | Analog Devices | |
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Data Sheet
High Performance, Low Power, ISM Band
FSK/GFSK/MSK/GMSK Transceiver IC
ADF7023-J
FEATURES
Ultralow power, high performance transceiver
Frequency bands: 902 MHz to 958 MHz
Data rates supported: 1 kbps to 300 kbps
2.2 V to 3.6 V power supply
Single-ended and differential power amplifiers (PAs)
Low IF receiver with programmable IF bandwidths
100 kHz, 150 kHz, 200 kHz, 300 kHz
Receiver sensitivity (BER)
−116 dBm at 1.0 kbps, 2FSK, GFSK
−107.5 dBm at 38.4 kbps, 2FSK, GFSK
−106.5 dBm at 50 kbps, 2FSK, GFSK
−105 dBm at 100 kbps, 2FSK, GFSK
−104 dBm at 150 kbps, GFSK, GMSK
−103 dBm at 200 kbps, GFSK, GMSK
−100.5 dBm at 300 kbps, GFSK, GMSK
Very low power consumption
12.8 mA in PHY_RX mode (maximum front-end gain)
11.9 mA in PHY_RX mode (AGC off, ADC off)
24.1 mA in PHY_TX mode (10 dBm output, single-ended PA)
0.75 µA in PHY_SLEEP mode (32 kHz RC oscillator active)
1.28 µA in PHY_SLEEP mode (32 kHz XTAL oscillator active)
0.33 µA in PHY_SLEEP mode (Deep Sleep Mode 1)
RF output power of −20 dBm to +13.5 dBm (single-ended PA)
RF output power of −20 dBm to +10 dBm (differential PA)
Patented fast settling automatic frequency control (AFC)
Digital received signal strength indication (RSSI)
Integrated PLL loop filter and Tx/Rx switch
Fast automatic voltage controlled oscillator (VCO) calibration
Automatic synthesizer bandwidth optimization
On-chip, low power, custom 8-bit processor
Radio control
Packet management
Smart wake mode
SPORT mode support
High speed synchronous serial interface to Tx and Rx Data
for direct interfacing to processors and DSPs
Packet management support
Highly flexible for a wide range of packet formats
Insertion/detection of preamble/sync word/CRC/address
Manchester and 8b/10b data encoding and decoding
Data whitening
Smart wake mode
Current saving low power mode with autonomous receiver
wake up, carrier sense, and packet reception
Downloadable firmware modules
Image rejection calibration, fully automated (patent
pending)
128-bit AES encryption/decryption with hardware
acceleration and key sizes of 128 bits, 192 bits, and
256 bits
Reed-Solomon error correction with hardware acceleration
240-byte packet buffer for Tx/Rx data
Efficient SPI control interface with block read/write access
Integrated battery alarm and temperature sensor
Integrated RC and 32.768 kHz crystal oscillator
On-chip, 8-bit ADC
5 mm × 5 mm, 32-lead, LFCSP package
APPLICATIONS
Smart metering
IEEE 802.15.4g
Home automation
Process and building control
Wireless sensor networks (WSNs)
Wireless healthcare
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF7023-J
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
ADCIN_ATB3
RFIO_1P
RFIO_1N
RFO2
LNA
PA
RSSI/
LOGAMP
8-BIT
ADC
FSK
ASK
DEMOD
CDR
AFC
AGC
PA DIVIDER
LOOP CHARGE
FILTER
PUMP
PFD
26MHz OSC
PA RAMP
PROFILE
ADF7023-J
DIVIDER
Σ-Δ
MODULATOR
fDEV
GAUSSIAN
FILTER
8-BIT RISC
PROCESSOR
4kB ROM
MAC
2kB RAM
256 BYTE
PACKET
RAM
64 BYTE
BBRAM
256 BYTE
MCR RAM
WAKE-UP CONTROL
TIMER UNIT
IRQ
CTRL
SPI
GPIO
TEST
DAC
CLOCK
DIVIDER
BIAS
ANALOG
TEST
TEMP
SENSOR
BATTERY
MONITOR
32kHz
OSC
32kHz
RCOSC
26MHz
OSC
IRQ_GP3
CS
MISO
SCLK
MOSI
GPIO1
CREGRFx CREGVCO CREGSYNTH CREGDIGx RBIAS
1GPIO REFERS TO PINS 17, 18, 19, 20, 25, AND 27.
XOSC32KN_ATB2 XOSC32KP_GP5_ATB1 XOSC26N XOSC26P
Figure 1.
GENERAL DESCRIPTION
The ADF7023-J is a very low power, high performance, highly
integrated 2FSK/GFSK/MSK/GMSK transceiver designed for
operation in the 902 MHz to 958 MHz frequency band, which
covers the ARIB Standard T96 band at 950 MHz. Data rates
from 1 kbps to 300 kbps are supported.
The transmit RF synthesizer contains a VCO and a low noise
fractional-N phase locked loop (PLL) with an output channel
frequency resolution of 400 Hz. The VCO operates at twice the
fundamental frequency to reduce spurious emissions. The receive
and transmit synthesizer bandwidths are automatically, and
independently, configured to achieve optimum phase noise,
modulation quality, and settling time. The transmitter output
power is programmable from −20 dBm to +13.5 dBm, with
automatic PA ramping to meet transient spurious specifications.
The part possesses both single-ended and differential PAs, which
allow for Tx antenna diversity.
The receiver is exceptionally linear, achieving an IP3 specification
of −12.2 dBm and −11.5 dBm at maximum gain and minimum
gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm
at maximum gain and minimum gain, respectively. The receiver
achieves an interference blocking specification of 66 dB at a
±2 MHz offset and 74 dB at a ±10 MHz offset. Thus, the part
is extremely resilient to the presence of interferers in spectrally
noisy environments. The receiver features a novel, high speed,
AFC loop, allowing the PLL to find and correct any RF frequency
errors in the recovered packet. A patent pending image rejection
calibration scheme is available by downloading the image rejection
calibration firmware module to program RAM. The algorithm
does not require the use of an external RF source nor does it
require any user intervention once initiated. The results of the
calibration can be stored in nonvolatile memory for use on
subsequent power-ups of the transceiver.
The ADF7023-J operates with a power supply range of 2.2 V to
3.6 V and has very low power consumption in both Tx and Rx
modes, enabling long lifetimes in battery-operated systems while
maintaining excellent RF performance. The device can enter a
low power sleep mode in which the configuration settings are
retained in the battery backup random access memory (BBRAM).
The ADF7023-J features an ultralow power, on-chip,
communications processor. The communications processor,
which is an 8-bit RISC processor, performs the radio control,
packet management, and smart wake mode (SWM) functionality.
The communications processor eases the processing burden of
the companion processor by integrating the lower layers of a
typical communication protocol stack. The communications
processor also permits the download and execution of firmware
modules. Available modules include image rejection (IR)
calibration, advanced encryption standard (AES) encryption,
and Reed-Solomon coding. These firmware modules are available
online at ftp://ftp.analog.com/pub/RFL/FirmwareModules.
The communications processor provides a simple command-based
radio control interface for the host processor. A single-byte command
transitions the radio between states or performs a radio function.
The communications processor provides support for generic
packet formats. The packet format is highly flexible and fully
programmable, thereby ensuring its compatibility with proprietary
packet profiles. In transmit mode, the communications processor
can be configured to add preamble, sync word, and CRC to the
payload data stored in packet RAM. In receive mode, the
Rev. D | Page 4 of 104
5 Page 
ADF7023-J
Parameter
GFSK/GMSK INPUT SENSITIVITY, PER
50 kbps
100 kbps
100 kbps
200 kbps
200 kbps
LNA AND MIXER, INPUT IP3
Minimum LNA Gain
Maximum LNA Gain
LNA AND MIXER, INPUT IP2
Maximum LNA Gain, Maximum Mixer Gain
Minimum LNA Gain, Minimum Mixer Gain
LNA AND MIXER, 1 dB COMPRESSION POINT
Maximum LNA Gain, Maximum Mixer Gain
Minimum LNA Gain, Minimum Mixer Gain
ADJACENT CHANNEL REJECTION
CW Interferer
±200 kHz Offset
+400 kHz Offset
−400 kHz Offset
CO-CHANNEL REJECTION
BLOCKING
RF Frequency = 954 MHz
±2 MHz
±10 MHz
±60 MHz
IMAGE CHANNEL ATTENUATION
954 MHz
Data Sheet
Min Typ
−104.1
−101.1
−102.2
−98.5
−99.5
−11.5
−12.2
18.5
27
−21.9
−21
38
51
33/39
−6
65
72
76
36/43.8
Max Unit Test Conditions/Comments
At PER = 1%, RF frequency = 954 MHz,
LNA and PA matched separately,
packet length = 20 octets, packet mode
dBm Frequency deviation = 25 kHz,
IF filter bandwidth = 100 kHz
dBm Frequency deviation = 50 kHz,
IF filter bandwidth = 100 kHz
dBm Frequency deviation = 40 kHz,
IF filter bandwidth = 100 kHz
dBm Frequency deviation = 100 kHz,
IF filter bandwidth = 200 kHz
dBm Frequency deviation = 80 kHz,
IF filter bandwidth = 200 kHz
Receiver LO frequency (fLO) = 914.8 MHz,
fSOURCE1 = fLO + 0.4 MHz, fSOURCE2 = fLO + 0.7 MHz
dBm
dBm
Receiver LO frequency (fLO) = 920.8 MHz,
fSOURCE1 = fLO + 1.1 MHz, fSOURCE2 = fLO + 1.3 MHz
dBm
dBm
RF frequency = 915 MHz
dBm
dBm
Desired signal at −87 dBm, CW interferer
power level increased until BER = 62−6,
image calibrated
dB IF BW = 100 kHz, wanted signal:
fDEV = 25 kHz, DR = 50 kbps
dB
dB Uncalibrated/internal calibration; using an
IF of 200 kHz, −400 kHz is the image frequency
dB Desired signal at −87 dBm,
data rate = 50 kbps,
frequency deviation = 25 kHz,
RF frequency = 954 MHz
Desired signal 3 dB above the input
sensitivity level, data rate = 50 kbps,
CW interferer power level increased until
BER = 10−3 (see the Typical Performance
Characteristics section for blocking at other
offsets and IF bandwidths), image calibrated
dB
dB
dB
Measured as image attenuation at the
IF filter output, carrier wave interferer at
400 kHz below the channel frequency,
100 kHz IF filter bandwidth
dB Uncalibrated/calibrated
Rev. D | Page 10 of 104
11 Page | ||
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