PDF ADF7025 Data sheet ( Hoja de datos )

Número de pieza	ADF7025
Descripción	High Performance ISM Band Transceiver IC
Fabricantes	Analog Devices
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Data Sheet High Performance ISM Band Transceiver IC ADF7025 FEATURES Low power, zero-IF RF transceiver Frequency bands 431 MHz to 464 MHz 862 MHz to 870 MHz 902 MHz to 928 MHz Data rates supported 9.6 kbps to 384 kbps, FSK 2.3 V to 3.6 V power supply Programmable output power −16 dBm to +13 dBm in 63 steps Receiver sensitivity −104.2 dBm at 38.4 kbps, FSK −100 dBm at 172.8 kbps, FSK −95.8 dBm at 384 kbps, FSK Low power consumption 19 mA in receive mode 28 mA in transmit mode (10 dBm output) RSET CREG(1:4) On-chip VCO and Fractional-N PLL On-chip, 7-bit ADC and temperature sensor Digital RSSI Integrated TRx switch Leakage current < 1 μA in power-down mode APPLICATIONS Wireless audio/video Remote control/security systems Wireless metering Keyless entry Home automation FUNCTIONAL BLOCK DIAGRAM ADCIN MUXOUT RLNA BIAS RFIN RFINB LNA GAIN LDO(1:4) OFFSET CORRECTION TEMP SENSOR TEST MUX LP FILTER RSSI MUX 7-BIT ADC FSK DEMODULATOR DATA SYNCHRONIZER OFFSET CORRECTION FSK MOD CONTROL Σ-∆ MODULATOR AGC CONTROL Tx/Rx CONTROL RFOUT DIVIDERS/ MUXING DIV P N/N+1 VCO CP PFD VCOIN CPOUT DIV R RING OSC CLK DIV OSC1 OSC2 Figure 1. SERIAL PORT CLKOUT CE DATA CLK DATA I/O INT/LOCK SLE SDATA SREAD SCLK Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet Parameter CHANNEL FILTERING Adjacent Channel Rejection (Offset = ±1 × LP Filter BW Setting) Second Adjacent Channel Rejection (Offset = ±2 × LP Filter BW Setting) Third Adjacent Channel Rejection (Offset = ±3 × LP Filter BW Setting) Co-Channel Rejection Wideband Interference Rejection BLOCKING ±1 MHz ±2 MHz ±10 MHz Saturation (Maximum Input Level) LNA Input Impedance Min RSSI Range at Input Linearity Absolute Accuracy Response Time PHASE-LOCKED LOOP VCO Gain Phase Noise (In-Band) Phase Noise (Out-of-Band) Residual FM PLL Settling Time REFERENCE INPUT Crystal Reference External Oscillator Load Capacitance Crystal Start-Up Time Input Level TIMING INFORMATION Chip Enabled to Regulator Ready Crystal Oscillator Startup Time Tx to Rx Turnaround Time 3.625 3.625 ADF7025 Typ Max 27 40 43 −2 +24 70 42 51 64 12 24 − j60 26 − j63 71 − j128 −100 to −36 ±2 ±3 150 65 83 −89 −110 128 40 24 24 33 1.0 10 1 150 µs + (5 × TBIT) Unit dB dB dB dB dB dB dB dB dBm Ω Ω Ω dBm dB dB µs MHz/V MHz/V dBc/Hz dBc/Hz Hz µs MHz MHz pF ms CMOS levels µs ms Test Conditions Desired signal (38.4 kbps DR, 200 kHz FDEV, ±300 KHz LP filter B/W) 6 dB above the input sensitivity level, CW interferer power level increased until BER = 10−3 Maximum rejection measured with CW interferer at center of channel Swept from 100 MHz to 2 GHz, measured as channel rejection Desired signal (38.4 kbps DR, 200 kHz FDEV, ±300 KHz LP filter B/W) 6 dB above the input sensitivity level, CW interferer power level increased until BER = 10−3 FSK mode, BER = 10−3 FRF = 915 MHz, RFIN to GND FRF = 868 MHz FRF = 433 MHz 902 MHz to 928 MHz band, VCO adjust = 3, VCO_BIAS_SETTING = 12 862 MHz to 870 MHz band, VCO adjust = 0, VCO_BIAS_SETTING = 10 PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz, FRF = 868 MHz, VCO_BIAS_SETTING = 10 1 MHz offset From 200 Hz to 20 kHz, FRF = 868MHz Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 20 MHz, LBW = 50kHz Using 33 pF load capacitors CREG = 100 nF With 19.2 MHz XTAL Time to synchronized data, includes AGC settling Rev. C \| Page 5 of 41 5 Page Data Sheet ADF7025 Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 to 47 48 Mnemonic GND2 ADCIN VREG2 VDD2 INT/LOCK DATA I/O DATA CLK CLKOUT MUXOUT OSC2 OSC1 VDD3 VREG3 CPOUT VDD GND CVCO EPAD Description Ground for Digital Section. Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to 1.9 V. Readback is made using the SREAD pin. Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin. Bidirectional Pin. In output mode (interrupt mode), the ADF7025 asserts the INT/LOCK pin when it has found a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked, NRZ data can be reliably received. In this mode, a demodulator lock can be asserted with minimum delay. Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply. In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the center of the received data. A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio. This pin provides the LOCK_DETECT signal, which is used to determine if the PLL is locked to the correct frequency. Other signals include REGULATOR_READY, which is an indicator of the status of the serial interface regulator. The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the crystal oscillator. The reference crystal should be connected between this pin and OSC2. Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a 0.01 µF capacitor. Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 µF capacitor. Grounds for VCO Block. A 22 nF capacitor should be placed between this pin and VREG1 to reduce VCO noise. Exposed Pad. Connect the exposed pad to GND. Rev. C \| Page 11 of 41 11 Page

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