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NXP Semiconductors |
74AVC16T245
16-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 01 — 1 October 2009
Product data sheet
1. General description
The 74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and
3-state outputs.The device can be used as two 8-bit transceivers or as a 16-bit
transceiver. It has dual supplies (VCC(A) and VCC(B)) for voltage translation and two 8-bit
input-output ports (nAn and nBn) each with its own output enable (nOE) and send/receive
(nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any
voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation
between any of the following voltages: 0.8 V,1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on
nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission
from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance
OFF-state
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both nAn and nBn are in the high-impedance OFF-state.
2. Features
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I Wide supply voltage range:
N VCC(A): 0.8 V to 3.6 V
N VCC(B): 0.8 V to 3.6 V
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3B exceeds 8000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Maximum data rates:
N 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
N 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
N 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
N 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
N 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
NXP Semiconductors
74AVC16T245
16-bit dual supply translating transceiver; 3-state
N 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
I Suspend mode
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74AVC16T245DGG −40 °C to +85 °C
TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
74AVC16T245DGV −40 °C to +85 °C
TSSOP48[1] plastic thin shrink small outline package; 48 leads; SOT480-1
body width 4.4 mm; lead pitch 0.4 mm
74AVC16T245EV
−40 °C to +125 °C VFBGA56 plastic very thin fine-pitch ball grid array package; SOT702-1
56 balls; body 4.5 × 7 × 0.65 mm
74AVC16T245BQ
−40 °C to +125 °C
HUQFN60U plastic thermal enhanced ultra thin quad flat
package; no leads; 60 terminals; UTLP based;
body 4 × 6 × 0.55 mm
SOT1025-1
[1] Also known as TVSOP48.
4. Functional diagram
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1DIR
1OE
2DIR
2OE
1A1
VCC(A)
VCC(B)
to other seven channels
1B1
Fig 1. Logic diagram
2A1
VCC(A)
VCC(B)
2B1
to other seven channels 001aak426
74AVC16T245_1
Product data sheet
Rev. 01 — 1 October 2009
© NXP B.V. 2009. All rights reserved.
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