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PDF ADM1487E Data sheet ( Hoja de datos )
| Número de pieza | ADM1487E | |
| Descripción | (ADMx48xE) transceivers | |
| Fabricantes | Analog Devices | |
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5 V, ±15 kV ESD Protected
Half-Duplex, RS-485/RS-422 Transceivers
ADM485E/ADM487E/ADM1487E
FEATURES
TIA/EIA RS-485-/RS-422-compliant
ESD protection on RS-485 I/O pins
±15 kV human body model
Data rates
ADM487E: 250 kbps
ADM485E/ADM1487E: 2.5 Mbps
Half-duplex options
Reduced slew rates for low EMI
−7 V to +12 V common-mode input range
Thermal shutdown and short-circuit protection
8-lead SOIC packages
APPLICATIONS
Energy/power metering
Lighting systems
Industrial control
Telecommunications
Security systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
VCC
ADM485E/
ADM487E/
ADM1487E
RO R
RE A
DE B
DI D
GND
Figure 1.
GENERAL DESCRIPTION
The ADM485E/ADM487E/ADM1487E are 5 V, low power
data transceivers with ±15 kV ESD protection suitable for half-
duplex communication on multipoint bus transmission lines.
They are designed for balanced data transmission and comply
with Telecommunication Industry Association/Electronics Indus-
tries Association (TIA/EIA) standards RS-485 and RS-422. The
ADM487E and ADM1487E have a 1/4 unit load receiver input
impedance that allows up to 128 transceivers on a bus, whereas
the ADM485E allows up to 32 transceivers on a bus. Because
only one driver is enabled at any time, the output of a disabled or
power-down driver is three-stated to avoid overloading the bus.
The driver outputs are slew rate-limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or output
shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the industrial temperature
ranges and are available in 8-lead SOIC packages.
Table 1. Selection Table
Part
Number
ADM485E
ADM487E
ADM1487E
Half-/Full-
Duplex
Half
Half
Half
Guaranteed
Data Rate
(Mbps)
2.5
0.25
2.5
Slew Rate
Limited
No
Yes
No
Low Power
Shutdown
No
Yes
No
Driver/Receiver
Enable
Yes
Yes
Yes
Quiescent
Current (μA)
300
120
230
Number of
Nodes on Bus
32
128
128
Pin
Count
8
8
8
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
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ADM485E/ADM487E/ADM1487E
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 4. ADM487E
Parameter
DRIVER
Input to Output
Output Skew to Output
Rise/Fall Time
Symbol Min
tDPLH
tDPHL
tSKEW
tDR, tDF
250
250
250
250
Enable Time to High Level
Enable Time to Low Level
Disable Time from Low Level
Disable Time from High Level
RECEIVER
Input to Output
tDZH
tDZL
tDLZ
tDHZ
tRPLH
tRPHL
250
300
300
250
250
|tPLH − tPHL| Differential Receiver Skew
tSKEW
Enable Time to Low Level
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
Maximum Data Rate
Time to Shutdown1
Driver Enable from Shutdown to Output High
Driver Enable from Shutdown to Output Low
Receiver Enable from Shutdown to Output High
tRZL
tRZL
tRLZ
tRHZ
fMAX
tDZH(SHDN)
tDZL(SHDN)
tRZL(SHDN)
tRZH(SHDN)
250
50
Typ Max Unit Test Conditions/Comments
800 2000 ns
800 2000 ns
20 800 ns
2000 ns
2000
2000
3000
3000
ns
ns
ns
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
CRL = 100 pF, S2 closed (see Figure 21)
CRL = 100 pF, S1 closed (see Figure 22)
CRL = 15 pF, S1 closed (see Figure 22)
CRL = 15 pF, S2 closed (see Figure 21)
100
25
25
25
25
200
5000
5000
5000
2000
2000
50
50
50
50
600
ns
ns
ns
ns
ns
ns
ns
kbps
ns
ns
ns
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
CRL = 15 pF, S1 closed
(see Figure 23 and Figure 24)
CRL = 15 pF, S2 closed (see Figure 25)
CRL = 15 pF, S1 closed (see Figure 25)
CRL = 15 pF, S2 closed (see Figure 25)
tPLH, tPHL < 50% of data period
CL = 100 pF, S2 closed (see Figure 21)
CL = 100 pF, S1 closed (see Figure 22)
CL = 15 pF, S2 closed (see Figure 25)
CL = 15 pF, S1 closed (see Figure 25)
1 The ADM487E is put into shutdown mode by bringing the RE high and the DE low. If the inputs are in this state for less than 50 ns, the parts are guaranteed not to
enter shutdown. If the inputs are in this state for at least 600 ns, the ADM487E is guaranteed to enter shutdown.
Rev. 0 | Page 5 of 16
5 Page 
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ADM485E/ADM487E/ADM1487E
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
Y
RL
VOD
RL VOC
Z
Figure 18. Driver DC Test Load
VDD
DE
A
DI
B
VOD
CL
RL
CL
0V OR 5V
D
GENERATOR
50Ω
DE
VCC
OUT
tDZL(StHDDZNL),
VOL
2.3V
VCC
RL = 500Ω
S1
OUT
CL
VCC/2
tDLZ
5V
0V
0.5V
Figure 19. Driver Timing Test Circuit
Figure 22. Driver Enable and Disable Times (tDZL, tDLZ, tDZL(SHDN))
5V
DI
0V
1.5V
tDPLH
tDPHL
B
VO
A
1/2VO
VDIFF
VO
0V
–VO
20%
tDR
VDIFF = V (A) – V (B)
80%
80%
tSKEW = tDPLH – tDPHL
Figure 20. Driver Propagation Delays
1/2 VO
20%
tDF
ATE
B RECEIVER
OUTPUT
VID R
A
Figure 23. Receiver Propagation Delay Test Circuit
A
B
VOH
RO
VOL
tRPLH
+1V
–1V
tRPHL
1.5V
THE RISE TIME AND FALL TIME OF INPUT A AND INPUT B < 4ns
Figure 24. Receiver Propagation Delays
0 OR 5V
D
S1
CL
OUT
RL = 500Ω
GENERATOR
50Ω
DE
tDZH(StHDDZNH),
OUT
2.3V
1.5V
5V
0V
0.5V
VOH
tDHZ
0V
Figure 21. Driver Enable and Disable Times (tDHZ, tDZH, tDZH(SHDN))
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADM1487E.PDF ] | |
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