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National Semiconductor |
www.DataSheet4U.com
August 1998
54AC646
Octal Transceiver/Register with TRI-STATE® Outputs
General Description
The ’AC646 consist of registered bus transceiver circuits,
with outputs, D-type flip-flops and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B bus
will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). The four fundamental data handling functions
available are illustrated in Figures 1, 2, 3, 4.
n Multiplexed real-time and stored data transfers
n TRI-STATE outputs
n 300 mil slim dual-in-line package
n Outputs source/sink 24 mA
n ’ACT646 has TTL compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC646: 5962-89682
Features
n Independent registers for A and B buses
Logic Symbols
DS100231-1
Pin Names
A0– A7
B0– B7
CPAB, CPBA
SAB, SBA
G
DIR
Description
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
IEEE/IEC
DS100231-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100231
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Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100231-3
Real Time Transfer
A-Bus to B-Bus
DS100231-7
FIGURE 1.
Real Time Transfer
B-Bus to A-Bus
DS100231-8
FIGURE 2.
Pin Assignment
for LCC
DS100231-4
Storage from
Bus to Register
DS100231-9
FIGURE 3.
Transfer from
Register to Bus
DS100231-10
FIGURE 4.
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