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Motorola Semiconductors |
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MC74AC646
MC74ACT646
Octal Transceiver/Register with
3ĆState Outputs (NonĆinverting)
The MC74AC646/74ACT646 consist of registered bus transceiver circuits,
with outputs, D-type flip-flops and control circuitry providing multiplexed transmission
of data directly from the input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition
of the appropriate clock pin (CAB or CBA). The four fundamental data handling
functions available are illustrated in the following figures.
OCTAL
TRANSCEIVER/REGISTER
WITH 3-STATE OUTPUTS
(NON-INVERTING)
REAL TIME TRANSFER
A-BUS TO B-BUS
A-BUS
REG REG
B-BUS
Figure 1
REAL TIME TRANSFER
B-BUS TO A-BUS
A-BUS
REG REG
B-BUS
Figure 2
STORAGE
FROM BUS TO REGISTER
A-BUS
REG REG
B-BUS
Figure 3
TRANSFER
FROM REGISTER TO BUS
A-BUS
REG REG
B-BUS
Figure 4
• Independent Registers for A and B Buses
• Multiplexed Real-Time and Stored Data Transfers
• Choice of True and Inverting Data Paths
• 3-State Outputs
• 300 mil Slim Dual In-Line Package
• Outputs Source/Sink 24 mA
• ′ACT646 Has TTL Compatible Inputs
N SUFFIX
CASE 724-03
PLASTIC
DW SUFFIX
CASE 751E-04
SOIC PACKAGE
LOGIC SYMBOL
CAB A0 A1 A2 A3 A4 A5 A6 A7
SAB
DIR
CBA
SBA
G B0 B1 B2 B3 B4 B5 B6 B7
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FACT DATA
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MC74AC646 MC74ACT646
FUNCTION TABLE
Inputs
G DIR CAB CBA SAB SBA
H X H or L H or L X X
HX
XX
Data I/O*
A0–A7
B0–B7
Input
Input
Operation or Function
Isolation
Store A and B Data
L LXXXL
L LXXXH
Output
Input
Real Time B Data to A Bus
Stored B Data to A Bus
L HXX L X
L H H or L X H X
Input
Output
Real Time A Data to B Bus
Stored A Data to B Bus
* The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus
pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
CAB 1
SAB 2
DIR 3
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
GND 12
24 VCC
23 CBA
22 SBA
21 G
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
G
DIR
CBA
SBA
CAB
SAB
A0
LOGIC DIAGRAM
1 OF 8 CHANNELS
D0
C0
D0
C0
B0
PIN NAMES
A0–A7
B0–B7
CAB, CBA
SAB, SBA
DIR, G
Data Register Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Inputs
TO 7 OTHER CHANNELS
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
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FACT DATA
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