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PDF MC74AC646 Data sheet ( Hoja de datos )

Número de pieza MC74AC646
Descripción OCTAL TRANSCEIVER/REGISTER
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MC74AC646, MC74ACT646
Octal Transceiver/Register
with 3-State Outputs
(Non-inverting)
The MC74AC646/74ACT646 consist of registered bus transceiver
circuits, with outputs, D−type flip−flops and control circuitry
providing multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B bus will be
loaded into the respective registers on the LOW−to−HIGH transition
of the appropriate clock pin (CAB or CBA). The four fundamental
data handling functions available are illustrated Figures 1 to 4.
Features
Independent Registers for A and B Buses
Multiplexed Real−Time and Stored Data Transfers
Choice of True and Inverting Data Paths
3−State Outputs
300 mil Slim Dual In−Line Package
Outputs Source/Sink 24 mA
ACT646 Has TTL Compatible Inputs
These are Pb−Free Devices
REAL TIME TRANSFER
A‐BUS TO B‐BUS
A‐BUS
REAL TIME TRANSFER
B‐BUS TO A‐BUS
A‐BUS
REG REG REG REG
B‐BUS
Figure 1.
B‐BUS
Figure 2.
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MARKING DIAGRAMS
24
1
SO−24
DW SUFFIX
CASE 751E
AC646
AWLYYWWG
ACT646
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
STORAGE
FROM BUS TO REGISTER
A‐BUS
REG REG
B‐BUS
Figure 3.
TRANSFER
FROM REGISTER TO BUS
A‐BUS
REG REG
B‐BUS
Figure 4.
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 7
1
Publication Order Number:
MC74AC646/D

1 page




MC74AC646 pdf
MC74AC646, MC74ACT646
DC CHARACTERISTICS
Symbol
Parameter
VIH Minimum High Level
Input Voltage
VIL Maximum Low Level
Input Voltage
VOH Minimum High Level
Output Voltage
74AC
74AC
VCC
(V)
TA = +25°C
TA =
−40°C to
+85°C
Typ Guaranteed Limits
3.0 1.5 2.1
4.5 2.25 3.15
5.5 2.75 3.85
2.1
3.15
3.85
3.0 1.5 0.9
4.5 2.25 1.35
5.5 2.75 1.65
0.9
1.35
1.65
3.0 2.99 2.9
4.5 4.49 4.4
5.5 5.49 5.4
2.9
4.4
5.4
Unit
V
V
V
VOL Maximum Low Level
Output Voltage
3.0 − 2.56
4.5 − 3.86
5.5 − 4.86
3.0 0.002 0.1
4.5 0.001 0.1
5.5 0.001 0.1
2.46
3.76
4.76
0.1
0.1
0.1
V
V
3.0 − 0.36
4.5 − 0.36
5.5 − 0.36
0.44
0.44
0.44
V
IIN Maximum Input
Leakage Current
5.5 − ±0.1
±1.0
μA
IOZT
Maximum
3-State
Current
5.5 − ±0.6
±6.0
μA
IOLD
IOHD
ICC
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5 − −
5.5 − −
5.5 − 8.0
75
−75
80
mA
mA
μA
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
Conditions
VOUT = 0.1 V
or VCC − 0.1 V
VOUT = 0.1 V
or VCC − 0.1 V
IOUT = −50 μA
*VIN = VIL or VIH
−12 mA
IOH −24 mA
−24 mA
IOUT = 50 μA
*VIN = VIL or VIH
12 mA
IOL 24 mA
24 mA
VI = VCC, GND
VI (OE) = VIL, VIH
VI = VCC, GND
VO = VCC, GND
VOLD = 1.65 V Max
VOHD = 3.85 V Min
VIN = VCC or GND
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