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STE100P 반도체 회로 부품 판매점

10/100 FAST ETHERNET 3.3V TRANSCEIVER



ST Microelectronics 로고
ST Microelectronics
STE100P 데이터시트, 핀배열, 회로
STE100P
10/100 FAST ETHERNET 3.3V TRANSCEIVER
1 DESCRIPTION
The STE100P, also referred to as STEPHY1, is a
high performance Fast Ethernet physical layer inter-
face for 10Base-T and 100Base-TX applications.
It was designed with advanced CMOS technology to
provide a Media Independent Interface (MII) for easy
attachment to 10/100 Media Access Controllers
(MAC) and a physical media interface for 100Base-
TX of IEEE802.3u and 10Base-T of IEEE802.3.
The STEPHY1 supports both half-duplex and full-du-
plex operation, at 10 and 100 Mbps operation. Its op-
erating mode can be set using auto-negotiation,
parallel detection or manual control. It also allows for
the support of auto-negotiation functions for speed
and duplex detection.
2 FEATURES
2.1 Industry standard
IEEE802.3u 100Base-TX and IEEE802.3
10Base-T compliant
Figure 2. Block Diagram
Figure 1. Package
TQFP64 (10x10x1.40mm)
Table 1. Order Codes
Part Number
STE100P
Package
TQFP64
Support for IEEE802.3x flow control
IEEE802.3u Auto-Negotiation support for
10Base-T and 100Base-TX
MII interface
Standard CSMA/CD or full duplex operation
supported
Industrial temperature compliant
LEDS
LEDS
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDC
MDIO
100Mb/s
4B/5B
TX Channel
Scrambler
Parallel to
Serial
NRZ To NRZI
Encoder
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Generator
REGISTERS
Auto
Negotiation
Binary To MLT3
Encoder
10 TX
Filter
Loopback
TRANSMITTER
10/100
TXP
TXN
Clock
Generation
System
Clock
RXD[3:0]
RX_ER
RX_DV
RX_CLK
HW
configuration
pins
HW Config
Power Down
100Mb/s
Descrambler
4B/5B Code Align
RX Channel
Serial to
Parallel
NRZI To NRZ
Decoder
Binary To MLT3
Decoder
Clock Recovery
Adaptive
Equalization
BaseLine
Wander
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Detector
10 TX Filter
Clock Recovery
SMART
Squelch
RECEIVER
10/100
RXP
RXN
September 2004
Rev. 18
1/31


STE100P 데이터시트, 핀배열, 회로
STE100P
2.2 Physical Layer
Integrates the whole Physical layer functions of 100Base-TX and 10Base-T
Provides Full-duplex operation on both 100Mbps and 10Mbps modes
Provides Auto-negotiation(NWAY) function of full/half duplex operation for both 10 and 100 Mbps
Provides MLT-3 transceiver with DC restoration for Base-line wander compensation
Provides transmit wave-shaper, receive filters, and adaptive equalizer
Provides loop-back modes for diagnostic
Builds in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder
Supports external transmit transformer with turn ratio 1:1
Supports external receive transformer with turn ratio 1:1
2.3 LED Display
The LED display, consists of five LEDs having the following characteristics:
10 Mbps Speed LED: 10Mbps(on) or 100Mbps(off)
100 Mbps Speed LED: 100Mbps(on) or 10Mbps(off)
TX/RX Activity LED: Blinks at 10Hz when receiving, but not colliding
Link LED: On when a good link is detected, blinks when there is TX or RX activity
Full Duplex / Collision LED: On during Full Duplex operation. Blinks at 20Hz to indicate a collision
2.4 Miscellaneous
Standard 64-pin QFP package pinout
Figure 3. System Diagram of the STE100P Application
Serial
EEPROM
LEDs
MAC
Device
STE100P
STEPHY1
Boot ROM
25 MHz
Crystal
RJ-45
2/31




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STE100P transceiver

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