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S3067TB20 반도체 회로 부품 판매점

Multirate Sonet / SDH / ATM Transceiver w/FEC



Applied Micro Circuits 로고
Applied Micro Circuits
S3067TB20 데이터시트, 핀배열, 회로
DEVICE
SMPUELCTIFIIRCAATTIEON(OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
SMBOUiCNLMETIOTR/SASDTLEHVP/(AOETCCM-L48OC/C2L4-O1/1C22K/3T/GRGEABNEES/FRMCAI)TTSTOOERNREATN/SDDRHE/ACTEMIVTERRANSCEIVER w/ FEC
®
S3067
SS33006677
FEATURES
• SiGe BiCMOS technology
• Complies with Bellcore and ITU-T
specifications
• On-chip high-frequency PLL for clock generation
• Supports:
- OC-48 (with FEC)
- OC-24 (with FEC)
- OC-12 (with FEC)
- OC-3 (with FEC)
- Fibre Channel
• FEC capability up to 8 bytes per 255-byte block
• Reference frequency – 131.25 MHz to 178 MHz
• Interface to LVPECL and TTL logic
• 16-Bit single-ended LVPECL data path
• Compact 156 Pin TBGA package
• Diagnostic loopback mode
• Supports line timing
• Lock Detect
• Signal detect input
• Low jitter LVPECL interface
• Internal FIFO to decouple transmit clocks
• Single 3.3 V supply
• Typical power 1.5 W
APPLICATIONS
• Wavelength Division Multiplexing equipment
• SONET/SDH-based transmission systems
• SONET/SDH modules
• SONET/SDH test equipment
• ATM over SONET/SDH
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broad-band cross-connects
• Fiber optic terminators
• Fiber optic test equipment
GENERAL DESCRIPTION
The S3067 SONET/SDH transceiver chip is a fully
integrated multirate serialization/deserialization SO-
NET OC-48, OC-24, OC-12 and OC-3 interface
device. The chip performs all necessary serial-to-
parallel and parallel-to-serial functions in
conformance with SONET/SDH transmission and
Forward Error Correction (FEC) standards. The de-
vice is suitable for SONET-based WDM applications.
Figure 1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3067
transceiver chip allowing the use of a slower external
transmit clock reference. The chip can be used with a
131.25 MHz to 178 MHz reference clock in support
of existing system clocking schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3067 is pack-
aged in a 156 Pin TBGA, offering designers a small
package outline.
The S3067 supports FEC designs with internal divid-
ers or external clocking modes.
Figure 1. System Block Diagram
2.488 Gbps
X
S3076
Clock
Recovery
Unit
2.488
Gbps
X
PERFORMANCE MONITOR
S3067
155 Mbps
Receive
Deserialization
X
S3062
Receive
S3062 167 Mbps S3067 2.67 Gbps
Transmit
FEC Added
X+Y
Transmit
Serialization X + Y
E/O
OPTICAL FIBER
PERFORMANCE MONITOR
O/E
S3076
S3067
S3062
Clock 2.67 Gbps Receive
167 Mbps Receive
Recovery X + Y Deserialization X + Y FEC Data
Unit Stripped Off
S3062
Transmit
155 Mbps
S3067
Transmit
2.488 Gbps
X Serialization X
X = Data
Y = FEC Data
September 17, 2002/ Revision A
1


S3067TB20 데이터시트, 핀배열, 회로
S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
SONET OVERVIEW
Synchronous Optical Network (SONET) is a stan-
dard for connecting one fiber system to another at
the optical level. SONET, together with the Synchro-
nous Digital Hierarchy (SDH) administered by the
ITU-T, forms a single international standard for fiber
interconnect between telephone networks of differ-
ent countries. SONET is capable of accommodating
a variety of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
• Photonic
• Section
• Line
• Path
Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to op-
tical and back with no overhead. It is responsible
for transmitting the electrical signals in optical form
over the physical media. The section layer handles
Figure 2. SONET Structure
Functions
Payload to
SPE mapping
Path layer
Maintenance,
protection,
switching
Line layer
Scrambling, Section layer
framing
Path layer
Line layer
Section layer
Optical Photonic layer
transmission
Photonic layer
End Equipment
Fiber Cable
End Equipment
Figure 3. STS–48/OC–48 Frame Format
the transport of the framed electrical signals across
the optical cable from one end to the next. Key
functions of this layer are framing, scrambling, and
error monitoring. The line layer is responsible for
the reliable transmission of the path layer informa-
tion stream, carrying voice, data, and video signals.
Its main functions are synchronization, multiplexing,
and reliable transport. The path layer is responsible
for the actual transport of services at the appropri-
ate signaling rates.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designa-
tions of the SONET hierarchy. The lowest level is the
basic SONET signal referred to as the synchronous
transport signal level-1 (STS-1). An STS-N signal is
made up of N-byte-interleaved STS-1 signals. The op-
tical counterpart of each STS-N signal is an optical
carrier level-N signal (OC-N). The S3067 chip sup-
ports up to the OC-48 rate with different FEC modes.
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for
STS-48 consists of 144 transport overhead bytes
followed by Synchronous Payload Envelope (SPE)
bytes. This pattern of 144 overhead and 4176 SPE
bytes is repeated nine times in each frame. Frame and
byte boundaries are detected using the A1 and A2
bytes found in the transport overhead. (See Figure 3.)
For more details on SONET operations, refer to the
Bellcore SONET standard document.
Table 1. SONET Signal Hierarchy
Elec.
STS-1
STS-3
STS-12
STS-24
STS-48
CCITT
STM-1
STM-4
STM-8
STM-16
Optical
OC-1
OC-3
OC-12
OC-24
OC-48
Data Rate (Mbps)
51.84
155.52
622.08
1244.16
2488.32
A1 A1
A1 A1
48 A1
Bytes
A2 A2
A2 A2
48 A2
Bytes
Transport Overhead 144 Columns
144 x 9 = 1296 bytes
125 µsec
Synchronous Payload Envelope 4176 Columns
4176 x 9 = 37,584 bytes
2 September 17, 2002/ Revision A




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