|
Fairchild Semiconductor |
March 2002
Revised June 2002
74LVT32245 • 74LVTH32245
Low Voltage 32-Bit Transceiver with 3-STATE Outputs
General Description
The LVT32245 and LVTH32245 contain thirty-two non-
inverting bidirectional buffers with 3-STATE outputs and are
intended for bus oriented applications. The devices are
byte controlled. Each byte has separate control inputs
which can be shorted together for full 32-bit operation. The
T/R inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVTH32245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low volt-
age (3.3V) VCC applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVT32245
and LVTH32245 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH32245),
also available without bushold feature (74LVT32245).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number Package Number
Package Description
74LVT32245G
(Note 1)(Note 2)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary)
74LVTH32245G
(Note 1)(Note 2)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500433
www.fairchildsemi.com
Connection Diagram
(Top Thru View)
Truth Tables
Inputs
OE1
L
L
H
T/R1
L
H
X
Inputs
OE2
T/R2
LL
LH
HX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Outputs
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH–Z State on A0–A7,B0–B7
Outputs
Bus B8–B15 Data to Bus A8–A15
Bus A8–A15 Data to Bus B8–B15
HIGH–Z State on A8–A15,B8–B15
Pin Descriptions
Pin Names
Description
OEn
T/Rn
A0–A31
B0–B31
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs/3-STATE Outputs
Side B Inputs/3-STATE Outputs
FBGA Pin Assignments
123456
A B1 B0 T/R1 OE1 A0 A1
B B3 B2 GND GND A2 A3
C B5 B4 VCC1 VCC1 A4 A5
D B7 B6 GND GND A6 A7
E B9 B8 GND GND A8 A9
F B11 B10 VCC1 VCC1 A10 A11
G B13 B12 GND GND A12 A13
H B14 B15 T/R2 OE2 A15 A14
J B17 B16 T/R3 OE3 A16 A17
K B19 B18 GND GND A18 A19
L B21 B20 VCC2 VCC2 A20 A21
M B23 B22 GND GND A22 A23
N B25 B24 GND GND A24 A25
P B27 B26 VCC2 VCC2 A26 A27
R B29 B28 GND GND A28 A29
T B30 B31 T/R4 OE4 A31 A30
Inputs
OE3
L
L
H
T/R3
L
H
X
Outputs
Bus B16–B23 Data to Bus A16–A23
Bus A16–A23 Data to Bus B16–B23
HIGH–Z State on A16–A23,B16–B23
Inputs
OE4
L
L
H
T/R4
L
H
X
Outputs
Bus B24–B31 Data to Bus A24–A31
Bus B24–A31 Data to Bus B24–B31
HIGH–Z State on A24–A31,B24–B31
www.fairchildsemi.com
2
|