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74HC646 반도체 회로 부품 판매점

Octal bus transceiver/register 3-state



Philips 로고
Philips
74HC646 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT646
Octal bus transceiver/register;
3-state
Product specification
File under Integrated Circuits, IC06
September 1993


74HC646 데이터시트, 핀배열, 회로
Philips Semiconductors
Octal bus transceiver/register; 3-state
Product specification
74HC/HCT646
FEATURES
Independent register for A and B buses
Multiplexed real-time and stored data
Output capability: bus driver
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT646 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT646 consist of bus transceiver circuits with
3-state outputs, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from
the internal registers. Data on the “A” or “B” bus will be
clocked into the registers as the appropriate clock
(CPAB and CPBA) goes to a HIGH logic level. Output
enable (OE) and direction (DIR) inputs are provided to
control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in
either the “A” or “B” register, or in both. The select source
inputs (SAB and SBA) can multiplex stored and real-time
(transparent mode) data. The direction (DIR) input
determines which bus will receive data when OE is active
(LOW). In the isolation mode (OE = HIGH), “A” data may
be stored in the “B” register and/or “B” data may be stored
in the “A” register.
When an output function is disabled, the input function is
still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time.
The “646” is functionally identical to the “648”, but has
non-inverting data paths.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL PARAMETER
CONDITIONS
tPHL/ tPLH
fmax
CI
CPD
propagation delay An, Bn to Bn, An
maximum clock frequency
input capacitance
power dissipation capacitance per channel
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
TYPICAL
HC
11
69
3.5
30
HCT
13
85
3.5
33
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993
2




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74HC646 transceiver

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