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74HC620 반도체 회로 부품 판매점

OCTAL BUS TRANSCEIVER HC620 3 STATE INVERTING HC623 3 STATE NON INVERTING



STMicroelectronics 로고
STMicroelectronics
74HC620 데이터시트, 핀배열, 회로
M54/74HC620
M54/74HC623
OCTAL BUS TRANSCEIVER
HC620 3 STATE INVERTING HC623 3 STATE NON INVERTING
. HIGH SPEED
tPD = 10 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 6 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V to 6 V
. PIN AND FUNCTION COMPATIBLE
WITH LS620/623
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R M74HCXXXM1R
M74HCXXXB1R M74HCXXXC1R
DESCRIPTION
The M54/74HC620/623 are high speed CMOS
OCTAL BUS TRANSCEIVERS fabricated in silicon
gate C2MOS technology. They have the same high
speed performance of LSTTL combined with true
CMOS low power consumption.
These octal bus transceivers are designed for asyn-
chronous two-way communication between data
buses. The control function implementation allows
maximum flexibility in timing.
These devices allow data transmission from the A
bus to B bus or from the B to the A bus depending
upon the logic levels at the enable inputs (GBA and
GAB). The enable inputs can be used to disable the
device so that the buses are effectively isolated.
The dual-enable configuration gives these devices
the capability to store data by simultaneous enabling
of GBA and GAB.
Each output reinforces its input in this transceiver
configuration. Thus, when both control inputs are
enabled and all other data sources to the two sets
of bus lines are at high impedance, both sets of bus
lines (16 in all) will remain at their last states. The 8-
bit codes appearing on the two sets of buses will be
identical for the ’HC623 or complementary for the
’HC620. All inputs are equipped with protection cir-
cuits against static discharge and transient excess
voltage.
October 1992
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
1/11


74HC620 데이터시트, 핀배열, 회로
M54/M74HC620/623
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
GAB
L
H
L
H
INPUTS
GBA
L
H
H
L
LOGIC DIAGRAM
FUNCTION
A Bus
B Bus
Output
Input
Input
Output
High Impedance
High Impedance
OUTPUS
HC620
HC623
A=B
A=B
B=A
B=A
ZZ
ZZ
2/11




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74HC620 transceiver

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74HC620

OCTAL BUS TRANSCEIVER HC620 3 STATE INVERTING HC623 3 STATE NON INVERTING - STMicroelectronics