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PDF 74F899 Data sheet ( Hoja de datos )
| Número de pieza | 74F899 | |
| Descripción | 9-Bit Latchable Transceiver with Parity Generator/Checker | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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February 1989
Revised August 1999
74F899
9-Bit Latchable Transceiver
with Parity Generator/Checker
General Description
The 74F899 is a 9-bit to 9-bit parity transceiver with trans-
parent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction. It has a guaranteed current
sinking capability of 24 mA at the A-bus and 64 mA at the
B-bus.
The 74F899 features independent latch enables for the
A-to-B direction and the B-to-A direction, a select pin for
ODD/EVEN parity, and separate error signal output pins for
checking parity.
Features
s Latchable transceiver with output sink of 24 mA at the
A-bus and 64 mA at the B-bus
s Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
s Independent latch enables for A-to-B and B-to-A
directions
s Select pin for ODD/EVEN parity
s ERRA and ERRB output pins for parity checking
s Ability to simultaneously generate and check parity
s May be used in systems applications in place of the
74F543 and 74F280
s May be used in system applications in place of the
74F657 and 74F373 (no need to change T/R to check
parity)
Ordering Code:
Order Number Package Number
Package Description
74F899SC
M28B
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F899QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignment for SOIC
Pin Assignment for PCC
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS010195
www.fairchildsemi.com
1 page  
DC Electrical Characteristics (Continued)
Symbol
Parameter
IIL+ Output Leakage
IOZL Current
IOS Output Short-Circuit Current
Min Typ
−60
IZZ
ICCH
ICCL
Bus Drainage Test
Power Supply Current
Power Supply Current
−100
132
178
ICCZ
Power Supply Current
160
AC Electrical Characteristics
Max
−650
−150
−225
500
155
210
190
Units
µA
mA
µA
mA
mA
mA
VCC
Max
Max
Max
0.0V
Max
Max
Max
Conditions
VI/O = 0.5V
(An, Bn, APAR, BPAR)
VOUT = 0V
(An, APAR, ERRA, ERRB)
VOUT = 0V (Bn, BPAR)
VOUT = 5.25V
VO = HIGH
VO = LOW, GAB = LOW,
GBA = HIGH, VIL = LOW
VO = HIGH Z
Symbol
Parameter
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tS(H)
tS(L)
tH(H)
tH(L)
tW
Propagation Delay
An, APAR to Bn, BPAR
Propagation Delay
An, Bn to BPAR, APAR
Propagation Delay
An, Bn to ERRA, ERRB
Propagation Delay
ODD/EVEN to ERRA, ERRB
Propagation Delay
ODD/EVEN to APAR, BPAR
Propagation Delay
APAR, BPAR to ERRA, ERRB
LEA/LEB to
ERRA /ERRB
Propagation Delay
SEL to APAR, BPAR
Propagation Delay
LEB to An, APAR
Propagation Delay
LEA to Bn, BPAR
Output Enable Time
GBA or GAB to An,
APAR or Bn, BPAR
Output Disable Time
GBA or GAB to An,
APAR or Bn, BPAR
Setup Time, HIGH or LOW
An, Bn to LEA, LEB
Hold Time, HIGH or LOW
An, Bn to LEA, LEB
Pulse Width for LEA, LEB
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Typ Max
4.0 7.5 13.0
4.0 8.5 13.0
7.5
12.0
17.0
7.5
12.5
17.0
7.5
12.0
17.0
7.5
12.5
17.0
4.5 7.5 11.0
4.5 8.0 11.0
4.5 7.5 11.5
4.5 8.5 11.5
5.5 9.0 13.0
5.5 9.5 13.0
9.5
13.0
17.5
9.7 17.5
3.0 6.0 10.0
3.0 7.0 10.0
3.5 7.0 10.0
3.5 8.0 10.0
3.5 6.5 10.0
3.5 7.5 10.0
1.0 4.5 10.0
1.0 6.5 10.0
1.0 4.0 7.0
1.0 4.0 7.0
5.0 1.6
5.0 1.8
0 −1.7
0 −1.5
6.0 2.0
TA = 0°C to +70°C
VCC = +5.0V
CL = 50 pF
Min Max
4.0 14.0
4.0 14.0
7.5 18.0
7.5 18.0
7.5 18.0
7.5 18.0
4.5 12.0
4.5 12.0
4.5 12.5
4.5 12.5
5.5 14.0
5.5 14.0
7.5 18.0
7.5 18.0
3.0 11.0
3.0 11.0
3.5 11.0
3.5 11.0
3.5 11.0
3.5 11.0
1.0 11.0
1.0 11.0
1.0 8.0
1.0 8.0
5.0
5.0
0
0
6.0
Units
Figure
Number
ns Figure 1
ns Figure 2
ns Figure 3
ns Figure 4
ns Figure 5
ns Figure 6
ns Figure 7
ns Figure 10
ns Figure 11
ns Figure 11
ns
Figure 8,
Figure 9
ns
Figure 8,
Figure 9
ns
Figure 12,
Figure 13
ns
Figure 12,
Figure 13
ns Figure 14
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M28B
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 74F899.PDF ] | |
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