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Transceivers/Registers



Fairchild 로고
Fairchild
74F651SPC 데이터시트, 핀배열, 회로
March 1988
Revised August 1999
74F651 • 74F652
Transceivers/Registers
General Description
These devices consist of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to HIGH
logic level. Output Enable pins (OEAB, OEBA) are pro-
vided to control the transceiver function.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data
s Choice of non-inverting and inverting data paths
74F651 inverting
74F652 non-inverting
Ordering Code:
Order Number Package Number
Package Description
74F651SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F651SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F652SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F652SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS009581
www.fairchildsemi.com


74F651SPC 데이터시트, 핀배열, 회로
Logic Symbols
74F651
IEEE/IEC
74F651
74F652
IEEE/IEC
74F652
Unit Loading/Fan Out
Pin Names
A0–A7, B0–B7
CPAB, CPBA
SAB, SBA
OEAB, OEBA
Description
A and B Inputs/
3-STATE Outputs
Clock Inputs
Select Inputs
Output Enable Inputs
U.L.
HIGH/LOW
1.0/1.0
600/106.6 (80)
1.0/1.0
1.0/1.0
1.0/1.0
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
12 mA/64 mA (48 mA)
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
Function Table
Inputs
Inputs/Outputs (Note 1)
OEAB OEBA CPAB CPBA SAB SBA A0 thru A7 B0 thru B7
Operating Mode
L H H or L H or L X X Input
Input
Isolation
 L H
XX
Store A and B Data
X H
H or L X X Input
Not Specified Store A, Hold B
 H H
X X Input
Output
Store A in Both Registers
L X H or L
X X Not Specified Input
Hold A, Store B
 L L
X X Output
Input
Store B in Both Registers
L L X X X L Output
Input
Real-Time B Data to A Bus
L L X H or L X H
Store B Data to A Bus
H H X X L X Input
Output
Real-Time A Data to B Bus
H H H or L X H X
Stored A Data to B Bus
H L H or L H or L H H Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
www.fairchildsemi.com
2




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