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Fairchild |
April 1988
Revised March 1999
74F543
Octal Registered Transceiver
General Description
The F543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. The A outputs are guaranteed to sink 24 mA while the
B outputs are rated for 64 mA.
Features
s 8-bit octal transceiver
s Back-to-back registers for storage
s Separate controls for data flow in each direction
s A outputs sink 24 mA
s B outputs sink 64 mA
Ordering Code:
Order Number Package Number
Package Description
74F543SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F543MSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F543SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009554.prf
www.fairchildsemi.com
Unit Loading/Fan Out
Pin Names
Description
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A0–A7
B0–B7
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/2.0
1.0/2.0
1.0/1.0
1.0/1.0
3.5/1.083
150/40 (33.8)
3.5/1.083
600/106.6 (80)
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−1.2 mA
20 µA/−1.2 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
70 µA/−650 µA
−3 mA/24 mA (20 mA)
70 µA/−650 µA
−12 mA/64 mA (48 mA)
Functional Description
The F543 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data
flow from A to B, for example, the A-to-B Enable (CEAB)
input must be LOW in order to enter data from A0–A7 or
take data from B0–B7, as indicated in the Data I/O Control
Table. With CEAB LOW, a LOW signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent;
a subsequent LOW-to-HIGH transition of the LEAB signal
puts the A latches in the storage mode and their outputs no
longer change with the A inputs. With CEAB and OEAB
both LOW, the 3-STATE B output buffers are active and
reflect the data present at the output of the A latches. Con-
trol of data flow from B to A is similar, but using the CEBA,
LEBA and OEBA inputs.
Logic Diagram
Data I/O Control Table
Inputs
CEAB LEAB OEAB
Latch
Status
Output
Buffers
HXX
Latched
High Z
XHX
Latched
—
L L X Transparent
—
XXH
—
High Z
LXL
—
Driving
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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