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ORT4622 반도체 회로 부품 판매점

Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver



Agere Systems 로고
Agere Systems
ORT4622 데이터시트, 핀배열, 회로
Preliminary Data Sheet
March 2000
ORCA® ORT4622 Field-Programmable System Chip (FPSC)
Four-Channel x 622 Mbits/s Backplane Transceiver
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of FPGA-based design implemen-
tation, coupled with high-speed serial backplane data
transfer. The 622 Mbits/s backplane transceiver
offers a clockless, high-speed interface for interde-
vice communication on a board or across a back-
plane. The built-in clock recovery of the ORT4622
allows for higher system performance, easier-to-
design clock domains in a multiboard system, and
fewer signals on the backplane. Network designers
will benefit from the backplane transceiver as a net-
work termination device. The backplane transceiver
offers SONET scrambling/descrambling of data and
streamlined SONET framing, pointer moving, and
transport overhead handling, plus the programmable
logic to terminate the network into proprietary sys-
tems. For non-SONET applications, all SONET func-
tionality is hidden from the user and no prior
networking knowledge is required.
Embedded Core Features
s Implemented in an ORCA Series 3 FPGA array.
s Allows wide range of applications for SONET net-
work termination application as well as generic data
moving for high-speed backplane data transfer.
s No knowledge of SONET/SDH needed in generic
applications. Simply supply data, 78 MHz clock, and
a frame pulse.
s High-speed interface (HSI) function for clock/data
recovery serial backplane data transfer without
external clocks.
Table 1. ORCA ORT4622—Available FPGA Logic
s HSI function uses Lucent Technologies Microelec-
tronics Group’s proven 622 Mbits/s serial interface
core.
s Four-channel HSI function provides 622 Mbits/s
serial interface per channel for a total chip band-
width of 2.5 Gbits/s (full duplex).
s LVDS I/Os compliant with EIA*-644, support hot
insertion.
s 8:1 data multiplexing/demultiplexing for 77.76 MHz
byte-wide data processing in FPGA logic.
s On-chip phase-lock loop (PLL) clock meets B jitter
tolerance specification of ITU-T Recommendation
G.958 (0.6 UIP-P at 250 kHz).
s Powerdown option of HSI receiver on a per-
channel basis.
s Highly efficient implementation with only 3% over-
head vs. 25% for 8B10B coding.
s In-Band management and configuration.
s Streamlined pointer processor (pointer mover) for
8 kHz frame alignment to system clocks.
s Built-in boundry scan (IEEE1149.1 JTAG).
s FIFOs align incoming data across all four channels
for STS-48 (2.5 Gbits/s) operation (in quad STS-12
format).
s 1 + 1 protection supports STS-12/STS-48 redun-
dancy by either software or hardware control for
protection switching applications.
* EIA is a registered trademark of Electronic Industries Associa-
tion.
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Device
ORT4622
Usable
System
Gates
60K—120K
Number of
LUTs
4032
Number of
Registers
5304
Max User
RAM
64K
Max User
I/Os
Array Size
Number of
PFUs
259 18 x 28 504
‡ The embedded core and interface are not included in the above gate counts. The usable gate count range from a logic-only gate count to
a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as
108 gates per PFU/SLIC), including 12 gates pre-LUT/FF pair (eight per PFU), and 12 gates per SLC/FF pair (one per PFU). Each of the
four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are
counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU.


ORT4622 데이터시트, 핀배열, 회로
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
Table of Contents
Contents
Page
Introduction ............................................................... 1
Embedded Core Features ......................................... 1
FPSC Highlights ........................................................ 4
Software Support ...................................................... 4
Description ................................................................ 5
What Is an FPSC? .................................................. 5
FPSC Overview ...................................................... 5
FPSC Gate Counting .............................................. 5
FPGA/Embedded Core Interface ............................ 5
ORCA Foundry Development System .................... 5
FPSC Design Kit ..................................................... 6
FPGA Logic Overview ............................................ 6
PLC Logic ............................................................... 6
PIC Logic ................................................................ 7
System Features .................................................... 7
Routing ................................................................... 7
Configuration .......................................................... 7
More Series 3 Information ...................................... 7
ORT4622 Overview ................................................... 8
Device Layout ......................................................... 8
Backplane Transceiver Interface ............................ 8
HSI Interface ........................................................... 10
STM Macrocell ........................................................ 10
CPU Interface ......................................................... 10
FPGA Interface ....................................................... 10
FPSC Configuration ................................................ 12
Generic Backplane Transceiver Application .............. 13
Backplane Transceiver Core Detailed Description .... 13
HSI Macro ............................................................... 13
STM Transmitter (FPGA -> Backplane) .................. 15
STM Receiver (Backplane -> FPGA) ...................... 19
Powerdown Mode ................................................... 25
Redundancy and Protection Switching ................... 25
Memory Map ............................................................. 26
Definition of Register Types ................................... 26
Memory Map Overview ........................................... 27
Powerup Sequencing for ORT4622 Device .............. 35
FPGA Configuration Data Format ............................. 36
Using ORCA Foundry to Generate Configuration
RAM Data ............................................................ 36
FPGA Configuration Data Frame ........................... 36
Bit Stream Error Checking ......................................... 38
FPGA Configuration Modes ...................................... 38
Absolute Maximum Ratings ....................................... 39
Recommend Operating Conditions ........................... 39
Electrical Characteristics ........................................... 40
HSI Circuit Specifications .......................................... 41
Input Data ............................................................... 41
Jitter Tolerance ....................................................... 41
Generated Output Jitter .......................................... 41
PLL ......................................................................... 41
Input Reference Clock ............................................ 41
HSI Circuit Specifications .......................................... 41
Lucent Technologies
Contents
Page
Power Supply Decoupling LC Circuit ...................... 42
LVDS I/O ................................................................... 43
LVDS Receiver Buffer Requirements ..................... 44
Timing Characteristics ............................................... 45
Description .............................................................. 45
PFU Timing ............................................................. 46
PLC Timing ............................................................. 46
SLIC Timing ............................................................ 46
PIO Timing .............................................................. 46
Special Function Timing ......................................... 46
Clock Timing ........................................................... 46
Configuration Timing ............................................... 46
Readback Timing .................................................... 46
Input/Output Buffer Measurement Conditions
(on-LVDS Buffer) ...................................................... 56
FPGA Output Buffer Characteristics ......................... 57
LVDS Buffer Characteristics ...................................... 58
Termination Resistor ............................................... 58
LVDS Driver Buffer Capabilities .............................. 58
Estimating Power Dissipation .................................... 59
ORT4622 Clock Power ........................................... 59
Pin Information .......................................................... 60
Package Thermal Characteristics Summary ............. 83
ΘJA ......................................................................... 83
ψJC ......................................................................... 83
ΘJC ......................................................................... 83
ΘJB ......................................................................... 83
FPGA Maximum Junction Temperature ................. 83
Package Thermal Characteristics ............................. 84
Package Coplanarity ................................................. 84
Package Parasitics .................................................... 84
Package Outline Diagrams ........................................ 86
Terms and Definitions ............................................. 86
432-Pin EBGA ........................................................ 87
680-Pin PBGAM ..................................................... 88
Ordering Information ................................................. 90
List of Figures
Figure 1. ORCA ORT4622 Block Diagram ................. 8
Figure 2. Architecture of ORT4622 Backplane
Transceiver .............................................................. 11
Figure 3. HSI Functional Block Diagram .................... 14
Figure 4. Byte Ordering of Input/Output Interface in
STS-12 Mode........................................................... 15
Figure 5. Interconnect of Streams for FIFO................ 20
Figure 6. Alignment of Four STS-12 Streams ............ 20
Figure 7. Examples of Link Alignment ........................ 21
Figure 8. Pointer Mover State Machine ...................... 22
Figure 9. SPE and C1J1 Functionality ....................... 24
Figure 10. SPE Stuff Bytes......................................... 25
Figure 11. Serial Configuration Data Format—
Autoincrement Mode................................................ 37
2




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Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver - Agere Systems