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PDF 74VHC161284 Data sheet ( Hoja de datos )
| Número de pieza | 74VHC161284 | |
| Descripción | IEEE 1284 Transceiver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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February 1998
Revised July 2000
74VHC161284
IEEE 1284 Transceiver
General Description
The VHC161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (± 14 mA). The pull-up and pull-
down series termination resistance of these outputs on the
cable side is optimized to drive an external cable. In addi-
tion, all inputs (except HLH) and outputs on the cable side
contain internal pull-up resistors connected to the VCC sup-
ply to provide proper termination and pull-ups for open
drain mode.
Outputs on the Peripheral side are standard LOW-drive
CMOS outputs. The DIR input controls data flow on the
A1–A8/B1–B8 transceiver pins.
Features
s Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
s Replaces the function of two (2) 74ACT1284 devices
s All inputs have hysteresis to provide noise margin
s B and Y output resistance optimized to drive external
cable
s B and Y outputs in high impedance mode during power
down
s Inputs and outputs on cable side have internal pull-up
resistors
s Flow-through pin configuration allows easy interface
between the Peripheral and Host
Ordering Code:
Ordering Number Package Number
Package Description
74VHC161284MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74VHC161284MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS500098
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
TA = −40°C to +85°C
Symbol
Parameter
VCC = 4.5V − 5.5V
Units
Min Max
tPHL
A1–A8 to B1–B8
tPLH
A1–A8 to B1–B8
tPHL
B1–B8 to A1–A8
tPLH
B1–B8 to A1–A8
tPHL
A9–A13 to Y9–Y13
tPLH
A9–A13 to Y9–Y13
tPHL
C14–C17 to A14–A17
tPLH
C14–C17 to A14–A17
tSKEW
LH-LH or HL-HL
tPHL
PLHIN to PLH
tPLH
PLHIN to PLH
tPHL
HLHIN to HLH
tPLH
HLHIN to HLH
tPHZ Output Disable Time
tPLZ DIR to A1–A8
tPZH Output Enable Time
tPZL DIR to A1–A8
tPHZ Output Disable Time
tPLZ DIR to B1–B8
tpEN Output Enable Time
HD to B1–B8, Y9–Y13
tpDis Output Disable Time
HD to B1–B8, Y9–Y13
tpEn–tpDis Output Enable-Output Disable
tSLEW
Output Slew Rate
tPLH
B1–B8, Y9–Y13
tPHL
tr, tf tRISE and tFALL
B1–B8, Y9–Y13 (Note 8)
Note 8: Open Drain
2.0 30.0 ns
2.0 30.0 ns
2.0 30.0 ns
2.0 30.0 ns
2.0 30.0 ns
2.0 30.0 ns
2.0 30.0 ns
2.0 30.0 ns
6.0 ns
2.0 30.0 ns
2.0 30.0 ns
2.0 30.0 ns
2.0 30.0 ns
2.0 18.0
ns
2.0 18.0
2.0 25.0
ns
2.0 25.0
2.0 25.0
ns
2.0 25.0
2.0 28.0 ns
2.0 28.0 ns
20.0
ns
0.05 0.40
V/ns
0.05 0.40
120
ns
120
Note 9: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type.
(i) A1–A8 to B1–B8, A9–Y13 to Y9–Y13
(ii) B1–B8 to A1–A8
(iii) C14–C17 to A14–A17
Note 10: This parameter is guaranteed but not tested, characterized only.
Figure
Number
Figure 1
Figure 2
Figure 3
Figure 3
Figure 1
Figure 2
Figure 3
Figure 3
(Note 9)
Figure 1
Figure 2
Figure 3
Figure 3
Figure 7
Figure 8
Figure 9
Figure 2
Figure 2
Figure 5
Figure 4
Figure 6
(Note 10)
Capacitance (Note 11)
Symbol
Parameter
CIN Input Capacitance
CI/O I/O Pin Capacitance
Note 11: Capacitance is measured at frequency = 1 MHz.
Typ Units
Conditions
5 pF VCC = 0.0V (HD, DIR, A9—A13, C14—C17, PLHIN and HLHIN)
12 pF VCC = 3.3V
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74VHC161284.PDF ] | |
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