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PDF 74VCXR162601 Data sheet ( Hoja de datos )
| Número de pieza | 74VCXR162601 | |
| Descripción | Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1998
Revised October 2004
74VCXR162601
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and
Outputs and 26Ω Series Resistors in the Outputs
General Description
The VCXR162601, 18-bit universal bus transceiver, com-
bines D-type latches and D-type flip-flops to allow data flow
in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. Output-enable OEAB is active-LOW. When OEAB
is HIGH, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The 74VCXR162601 is designed for low voltage (1.4V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The VCXR162601 is also designed with 26Ω series resis-
tors on both the A and B Port outputs. This design reduces
line noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
Features
s 1.4V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26Ω series resistors on both the A and B Port outputs.
s tPD (A to B, B to A)
3.8 ns max for 3.0V to 3.6V VCC
s Power-down HIGH impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Static Drive (IOH/IOL)
±12 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latchup performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
Package
Number
Package Description
74VCXR162601MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2004 Fairchild Semiconductor Corporation DS500171
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
Conditions
VCC TA = −40°C to +85°C
Figure
Units
(V) Min Max
Number
fMAX
Maximum Clock Frequency
CL = 30 pF
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
250
200
100
MHz
tPHL Propagation Delay
tPLH A to B or B to A
CL = 15 pF
CL = 30 pF, RL = 500Ω
1.5 ± 0.1
80.0
3.3 ± 0.3
0.6
3.8
2.5 ± 0.2
0.8
4.6
Figures
1, 2
1.8 ± 0.15
1.5
9.2
ns
CL = 15 pF, RL = 2kΩ
1.5 ± 0.1
1.0
18.4
Figures
7, 8
tPHL Propagation Delay
tPLH Clock to A or B
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
0.6
4.4
2.5 ± 0.2
0.8
5.5
Figures
1, 2
1.8 ± 0.15
1.5
9.8
ns
CL = 15 pF, RL = 500Ω
1.5 ± 0.1
1.0
19.6
Figures
7, 8
tPHL Propagation Delay
tPLH LEBA or LEAB to A or B
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
0.6
4.4
2.5 ± 0.2
0.8
5.8
Figures
1, 2
1.8 ± 0.15
1.5
9.8
ns
CL = 15 pF, RL = 500Ω
1.5 ± 0.1
1.0
19.6
Figures
7, 8
tPZL Output Enable Time
tPZH OEBA or OEAB to A or B
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
0.6
4.3
2.5 ± 0.2
0.8
5.9
Figures
1, 3, 4
1.8 ± 0.15
1.5
9.8
ns
CL = 15 pF, RL = 2kΩ
1.5 ± 0.1
1.0
19.6
Figures
7, 9, 10
tPLZ Output Disable Time
tPHZ OEBA or OEAB to A or B
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
0.6
4.3
2.5 ± 0.2
0.8
4.9
Figures
1, 3, 4
1.8 ± 0.15
1.5
8.8
ns
CL = 15 pF, RL = 2kΩ
1.5 ± 0.1
1.0
17.6
Figures
7, 9, 10
tS Setup Time
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5
1.5
2.5
ns Figure 6
tH Hold Time
CL = 15 pF, RL = 500Ω
CL = 30 pF, RL = 500Ω
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
3.0
1.0
1.0
1.0
ns Figure 6
tW Pulse Width
CL = 15 pF, RL = 500Ω
CL = 30 pF, RL = 500Ω
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
2.0
1.5
1.5
4.0
ns Figure 5
tOSHL
tOSLH
Output to Output Skew
(Note 10)
CL = 15 pF, RL = 500Ω
CL = 30 pF, RL = 500Ω
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
4.0
0.5
0.5
0.75
ns
CL = 15 pF, RL = 2kΩ
Note 9: For CL = 50 pF, add approximately 300 ps to the AC maximum specification.
1.5 ± 0.1
1.5
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
5 www.fairchildsemi.com
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