|
Fairchild Semiconductor |
November 1999
Revised May 2000
74LVTH646
Low Voltage Octal Transceiver/Register
with 3-STATE Outputs
General Description
The LVTH646 consists of registered bus transceiver cir-
cuits, D-type flip-flops, and control circuitry providing multi-
plexed transmission of data directly from the input bus or
from the internal storage registers. Data on the A or B bus
will be loaded into the respective registers on the LOW-to-
HIGH transition of the appropriate clock pin (CPAB or
CPBA). (See Functional Description)
The LVTH646 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
The bus transceivers are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH646 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 646
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH646WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVTH646MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation DS012017
www.fairchildsemi.com
Connection Diagram
Pin Descriptions
Pin Names
A0–A7
B0–B7
CPAB, CPBA
SAB, SBA
OE
DIR
Description
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
Truth Table
(Note 1)
Inputs
Data I/O
OE DIR CPAB CPBA SAB SBA A0–A7 B0–B7
Function
H X H or L H or L X
H X
XX
H X
X
X
LH
LH
X
XL
XL
L H H or L
LH
X
X
H
H
LL
LL
X
X
X X
X
LL
LL
X H or L X
XX
H = HIGH Voltage Level L = LOW Voltage Level
X Isolation
X Input Input Clock An Data into A Register
X Clock Bn Data into B Register
X An to Bn—Real Time (Transparent Mode)
X Input Output Clock An Data into A Register
X A Register to Bn (Stored Mode)
X Clock An Data into A Register and Output to Bn
L Bn to An—Real Time (Transparent Mode)
L Output Input Clock Bn Data into B Register
H B Register to An (Stored Mode)
H
X = Immaterial
Clock Bn Data into B Register and Output to An
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
|