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74LVT543 반도체 회로 부품 판매점

3.3V Octal latched transceiver with dual enable 3-State



NXP Semiconductors 로고
NXP Semiconductors
74LVT543 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74LVT543
3.3V Octal latched transceiver with
dual enable (3-State)
Product specification
Supersedes data of 1994 May 20
IC23 Data Handbook
1998 Feb 19
Philips
Semiconductors


74LVT543 데이터시트, 핀배열, 회로
Philips Semiconductors
3.3V Octal latched transceiver with dual enable
(3-State)
Product specification
74LVT543
FEATURES
Combines 74LVT245 and 74LVT373 type functions in one device
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Output capability: +64mA/–32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
No bus current loading when output is tied to 5V bus
Power-up 3-State
Power-up reset
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74LVT543 is a high-performance BiCMOS product designed for
VCC operation at 3.3V.
This device contains two sets of D-type latches for temporary
storage of data flowing in either direction. Separate Latch Enable
(LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are
provided for each register to permit independent control of data
transfer in either direction. The outputs are guaranteed to sink
64mA.
FUNCTIONAL DESCRIPTION
The 74LVT543 contains two sets of eight D–type latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB) input and the A-to-B Latch
Enable (LEAB) input are Low the A-to-B path is transparent. A
subsequent Low-to-High transition of the LEAB signal puts the A
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB and OEAB both Low, the
3-State B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B to A is similar, but using the EBA, LEBA,
and OEBA inputs.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
CI/O
ICCZ
Propagation delay
An to Bn or Bn to An
Input capacitance
I/O capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF;
VCC = 3.3V
VI = 0V or 3.0V
Outputs disabled; VI/O = 0V or 3.0V
Outputs disabled; VCC = 3.6V
TYPICAL
2.3
3.0
4
10
0.13
UNIT
ns
pF
pF
mA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic SOL
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT543 D
74LVT543 DB
74LVT543 PW
NORTH AMERICA
74LVT543 D
74LVT543 DB
74LVT543PW DH
DWG NUMBER
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
LOGIC SYMBOL
LEBA 1
OEBA 2
A0 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
EAB 11
GND 12
24 VCC
23 EBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
SV00026
3 4 5 6 7 8 9 10
A0 A1 A2 A3 A4 A5 A6 A7
11 EAB
23 EBA
14 LEAB
1 LEBA
OEAB
OEBA
13
2
B0 B1 B2 B3 B4 B5 B6 B7
22 21 20 19 18 17 16 15
SV00027
1998 Feb 19
2 853-1749 18988




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74LVT543 transceiver

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