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Fairchild Semiconductor |
January 1999
Revised November 1999
74LVT16245 • 74LVTH16245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
General Description
The LVT16245 and LVTH16245 contain sixteen non-invert-
ing bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVTH16245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low-volt-
age (3.3V) VCC applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVT16245
and LVTH16245 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH16245), also
available without bushold feature (74LVT16245).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 16245
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
Package
Number
Package Description
74LVT16245MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT16245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16245MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVTH16245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS500152
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Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
T/Rn
A0–A15
B0–B15
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs/3-STATE Outputs
Side B Inputs/3-STATE Outputs
Truth Tables
Inputs
OE1
L
L
H
T/R1
L
H
X
Outputs
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH–Z State on A0–A7,B0–B7
Inputs
OE2
T/R2
LL
LH
HX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Outputs
Bus B8–B15 Data to Bus A8–A15
Bus A8–A15 Data to Bus B8–B15
HIGH–Z State on A8–A15,B8–B15
Functional Description
The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte
controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to
obtain full 16-bit operation.
Logic Diagrams
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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