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74LVC646A 반도체 회로 부품 판매점

Octal bus transceiver/register 3-State



NXP Semiconductors 로고
NXP Semiconductors
74LVC646A 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74LVC646A
Octal bus transceiver/register (3-State)
Product specification
Supercedes data of 1998 Mar 25
IC24 Data Handbook
1998 Jul 29
Philips
Semiconductors


74LVC646A 데이터시트, 핀배열, 회로
Philips Semiconductors
Octal bus transceiver/register (3-State)
Product specification
74LVC646A
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Flow-through pin-out architecture
In accordance with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC646A is a high performance, low-power, low-voltage
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC646A consist of non-inverting bus transceiver circuits
with 3-State outputs, D-type flip-flops and control circuitry arranged
for multiplexed transmission of data directly from the internal
registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal
registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH
logic level. Output enable (OE) and direction (DIR) inputs are
provided to control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in either the
‘A’ or ‘B’ register, or in both. The select source inputs (SAB and
SBA) can multiplex stored and real-time (transparent mode) data.
The direction (DIR) input determines which bus will receive data
when OE is active (LOW). In the isolation mode (OE = HIGH), ‘A’
data may be stored in the ‘B’ register and/or ‘B’ data may be stored
in the ‘A’ register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, ‘A’ or ‘B’ may be driven at a time.
The ‘646A’ is functionally identical to the ‘648A’ but has non-inverting
data paths.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
fmax
CI
CI/O
CPD
Propagation delay
An to Yn
Maximum clock frequency
Input capacitance
Input/output capacitance
Power dissipation capacitance per gate
CL = 50pF
VCC = 3.3V
Notes 1, 2
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 x fi )Σ (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL VCC2 fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
TYPICAL
3.9
250
5.0
10
26
UNIT
ns
MHz
pF
pF
pF
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
24-Pin Plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH
AMERICA
74LVC646A D
74LVC646A DB
74LVC646A PW
NORTH AMERICA
74LVC646A D
74LVC646A DB
7LVC646APW DH
PKG. DWG. #
SOT137-1
SOT340-1
SOT355-1
1998 Jul 29
2 853-2105 19803




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