32-bit bus transceiver with direction pin; 30 Ω
series termination resistors; 5 V tolerant; 3-state
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range of 1.2 to 3.6 V
• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
• MULTIBYTE™ flow-trough standard pin-out architecture
• Low inductance multiple power and ground pins for
minimum noise and ground bounce
• Direct interface with TTL levels
• Bus hold on data inputs (74LVCH322245A only)
• Integrated 30 Ω termination resistors
• Typical output ground bounce voltage:
VOLP <0.8 V at VCC = 3.3 V; Tamb = 25 °C
• Typical output VOH undershoot voltage:
VOHV >2 V at VCC = 3.3 V; Tamb = 25 °C
• Power-off disabled outputs, permitting live insertion
• Plastic fine-pitch ball grid array package.
The 74LVC(H)322245A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of
these devices in a mixed 3.3 and 5 V environment.
The 74LVC(H)322245A is a 32-bit transceiver featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions. The 74LVC(H)322245A features
two output enable (nOE) inputs for easy cascading and
two send or receive (nDIR) inputs for direction control.
nOE controls the outputs so that the buses are effectively
isolated. The 74LVC(H)322245A is designed with 30 Ω
series termination resistors in both HIGH and LOW output
stages to reduce line noise.
To ensure the high-impedance state during power-up or
power-down, input nOE should be tied to VCC through a
pull-up resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
The 74LVCH322245A bus hold data inputs eliminates the
need for external pull-up resistors to hold unused or
floating data inputs at a valid logic level (see Fig.2).
QUICK REFERENCE DATA
Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
nAn to nBn; nBn to nAn
power dissipation capacitance per
CL = 50 pF; VCC = 3.3 V
VI = GND to VCC; note 1
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
1999 Sep 01