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Fairchild Semiconductor |
March 2002
Revised March 2002
74LCXZ16245
Low Voltage 16-Bit Bidirectional Transceiver
with 5V Tolerant Inputs and Outputs
General Description
The LCXZ16245 contains sixteen non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus
oriented applications. The device is designed for low volt-
age (2.7V or 3.3V) VCC applications with capability of inter-
facing to a 5V signal environment. The device is byte
controlled. Each byte has separate control inputs which
could be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
When VCC is between 0V and 1.5V, the LCXZ16245 is on
the high impedance state during power-up or power-down.
This places the outputs in the high impedance (Z) state
preventing intermittent low impedance loading or glitching
in bus oriented applications.
The LCXZ16245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.7V–3.6V VCC specifications provided
s 4.5 ns tPD max (VCC = 3.3V), 20 µA ICC max
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance conforms to the requirements of
JESD78
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCXZ16245GX
(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74LCXZ16245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 2: BGA package available in Tape and Reel only.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500580
www.fairchildsemi.com
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
Pin Names
OEn
T/Rn
A0–A15
B0–B15
NC
Description
Output Enable Input
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
No Connect
FBGA Pin Assignments
12
A B0 NC
B B2 B1
C B4 B3
H B6 B5
E B8 B7
F B10 B9
G B12 B11
H B14 B13
J B15 NC
Truth Tables
3
T/R1
NC
VCC
GND
GND
GND
VCC
NC
T/R2
4
OE1
NC
VCC
GND
GND
GND
VCC
NC
OE2
5
NC
A1
A3
A5
A7
A9
A11
A13
NC
6
A0
A2
A4
A6
A8
A10
A12
A14
A15
Inputs
OE1
L
L
H
T/R1
L
H
X
Outputs
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH Z State on A0–A7, B0–B7
Inputs
OE2
T/R2
LL
LH
HX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Outputs
Bus B8–B15 Data to Bus A8–A15
Bus A8–A15 Data to Bus B8–B15
HIGH Z State on A8–A15, B8–B15
Logic Diagram
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