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74LCX652MTC 반도체 회로 부품 판매점

Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74LCX652MTC 데이터시트, 핀배열, 회로
February 1994
Revised April 1999
74LCX652
Low Voltage Transceiver/Register with 5V Tolerant
Inputs and Outputs
General Description
The LCX652 consists of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to the
HIGH logic level. Output Enable pins (OEAB, OEBA) are
provided to control the transceiver function.
The LCX652 is designed for low voltage (2.5V or 3.3V) VCC
applications with capability of interfacing to a 5V signal
environment.
The LCX652 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V 3.6V VCC specifications provided
s 7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCX652WM
74LCX652MSA
74LCX652MTC
Package Number
Package Description
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A0–A7, B0–B7
CPAB, CPBA
SAB, SBA
OEAB, OEBA
Description
A and B Inputs/3-STATE Outputs
Clock Inputs
Select Inputs
Output Enable Inputs
© 1999 Fairchild Semiconductor Corporation DS011998.prf
www.fairchildsemi.com


74LCX652MTC 데이터시트, 핀배열, 회로
Logic Symbols
IEEE/IEC
Truth Table
(Note 2)
Inputs
Inputs/Outputs
Operating Mode
OEAB OEBA CPAB CPBA SAB SBA A0 thru A7
B0 thru B7
L H H or L H or L X X Input
Input
Isolation
 L H
XX
Store A and B Data
X H
H or L X
X Input
Not Specified Store A, Hold B
 H H
X X Input
Output
Store A in Both Registers
L X H or L
X X Not Specified Input
Hold A, Store B
 L L
X X Output
Input
Store B in Both Registers
LL
X
X X L Output
Input
Real-Time B Data to A Bus
LL
X
H or L X
H
Store B Data to A Bus
HH
X
X L X Input
Output
Real-Time A Data to B Bus
H H H or L X
HX
Stored A Data to B Bus
H L H or L H or L H H Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Note 2: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
www.fairchildsemi.com
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74LCX652MTC transceiver

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74LCX652MTC

Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs - Fairchild Semiconductor