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18-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74LCX16501MTD 데이터시트, 핀배열, 회로
October 1995
Revised April 1999
74LCX16501
18-Bit Universal Bus Transceivers with 5V Tolerant
Inputs and Outputs
General Description
The LCX16501 is an 18-bit universal bus transceiver com-
bining D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LCX16501 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment.
The LCX16501 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power.
Features
s 5V tolerant inputs and outputs
s 2.3V–3.6V VCC specifications provided
s 6.0 ns tPD max (VCC = 3.3V), 20 µA ICC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA Output Drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model < 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC and OE tied to GND through a resistor: the minimum
value or the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX16501MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCX16501MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS012550.prf
www.fairchildsemi.com


74LCX16501MTD 데이터시트, 핀배열, 회로
Connection Diagram
Truth Table (Note 2)
OEAB
L
Inputs
LEAB CLKAB
XX
An
X
Output
Bn
Z
HHX L
L
HHXH
H
HL L
L
HL H
H
H L H X B0 (Note 3)
H L L X B0 (Note 4)
Note 2: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA.
Note 3: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was HIGH before LEAB went LOW.
Note 4: Output level before the indicated steady-state input conditions
were established.
Functional Description
For A-to-B data flow, the LCX16501 operates in the trans-
parent mode when LEAB is HIGH. When LEAB is LOW,
the A data is latched if CLKAB is held at a high or low logic
level. If LEAB is LOW, the A bus data is stored in the latch/
flip-flop on the LOW-to-HIGH transition of CLKAB. When
Logic Diagram
OEAB is HIGH, the outputs are active. When OEAB is
LOW, the outputs are in the high impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
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74LCX16501MTD transceiver

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18-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs - Fairchild Semiconductor