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PDF TZA3005H Data sheet ( Hoja de datos )
| Número de pieza | TZA3005H | |
| Descripción | SDH/SONET STM1/OC3 and STM4/OC12 transceiver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
TZA3005H
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
Product specification
Supersedes data of 1997 Aug 05
File under Integrated Circuits, IC19
2000 Feb 17
1 page  
Philips Semiconductors
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
SYMBOL
PIN TYPE(1)
DESCRIPTION
RXPD4
GNDRXOUT
RXPD5
RXPD6
RXPD7
VCC(RXOUT)
RXPCLK
MRST
MODE
ALTPIN
GNDTXCORE
VCC(TXCORE)
TXPD0
TXPD1
TXPD2
TXPD3
TXPD4
TXPD5
TXPD6
TXPD7
TXPCLK
SYNCLKDIV
LOCKDET
19MHZO
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
O parallel data output 4
G ground (receiver output)
O parallel data output 5
O parallel data output 6
O parallel data output 7
S supply voltage (receiver output)
O receive parallel clock output
I master reset (active LOW)
I serial data rate select STM1/STM4
I test and control input
G ground (transmitter core)
S supply voltage (transmitter core)
I parallel data input 0
I parallel data input 1
I parallel data input 2
I parallel data input 3
I parallel data input 4
I parallel data input 5
I parallel data input 6
I parallel data input 7
I transmit parallel clock input
O transmit byte/nibble clock output (synchronous)
O lock detect output
O 19 MHz reference clock output
Note
1. Pin type abbreviations: O = Output, I = Input, S = Supply, G = Ground.
Product specification
TZA3005H
2000 Feb 17
5
5 Page 
Philips Semiconductors
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
Product specification
TZA3005H
Other operating modes
DIAGNOSTIC LOOPBACK
A transmitter-to-receiver loopback mode is available for
diagnostic purposes. When DLEN is LOW, the differential
serial clock and data from the transmitter parallel-to-serial
block continue to be routed to transmitter outputs, but are
also routed to the receiver serial-to-parallel block instead
of the receiver input signals from pins RXSD/RXSDQ and
RXSCLK/RXSCLKQ.
LINE LOOPBACK
A receiver-to-transmitter loopback mode is available for
line testing purposes. When LLEN is LOW, the receiver
input signals (RXSD/RXSDQ and RXSCLK/RXSCLKQ)
are routed, after retiming, to the transmitter output buffers.
The receiver clock and data are also routed to the
serial-to-parallel block.
LOOP TIMING
In loop timing mode, the transmitter section is clocked by
the receiver input clock (RXSCLK) instead of by the
internal clock synthesizer. SYNCLKDIV is now derived
from RXSCLK so that it can be used to clock upstream
transmitter logic. Loop timing is enabled by setting pins
ALTPIN, TEST1, TEST2 and TEST3 (see Table 6). After
activating the loop timing mode, the receiver clock must be
synchronized to the transmitter input data
(TXPD0 to TXPD7) by activating master reset (MRST).
In loop timing mode, the internal clock synthesizer is still
used to generate the 19MHz output clock signal on
pin 19MHZO.
SQUELCHED CLOCK OPERATION
Some clock recovery devices force their recovered output
clock to zero if a loss of input signal is detected. If this
happens, the SDTTL or SDPECL signals are inactive and
no clock signal is present at pins RXSCLK and RXSCLKQ.
If no clock signal is present at pins RXSCLK/RXSCLKQ,
there is no RXPCLK signal. This may not be suitable for
some applications, in which case, the TZA3005H can be
set to squelched clock operation by setting pins ALTPIN,
TEST1, TEST2 and TEST3 as shown in Table 6.
In squelched clock operation, receiver timing is performed
by a part of the internal clock synthesizer which normally
only provides transmitter timing. This produces a RXPCLK
clock signal when either SDTTL or SDPECL is inactive. If
either SDTTL or SDPECL is inactive in squelched clock
operation, it is equivalent to normal operation. During a
transition from normal operation to squelched clock
operation, the RXPCLK clock cycle exhibits a once-only
random shortening.
Table 6 shows that the same operating mode can be
selected at different settings of the control inputs.
If ALTPIN = 0, the STM4 nibble mode is not available, but
is used for squelched clock operation. If ALTPIN = 1, all
operating modes are available, including STM4 nibble
mode.
2000 Feb 17
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet TZA3005H.PDF ] | |
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