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PDF 7006 Data sheet ( Hoja de datos )
| Número de pieza | 7006 | |
| Descripción | ACT7005/7006 Single Package Solution Dual Transceiver/ Protocol/ Subsystem | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 7006 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
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ACT7005/7006
Single Package Solution
Dual Transceiver, Protocol, Subsystem
Features
• Incorporates Transceivers, Protocol, and System Interface Components into a
Single Hybrid Package
• Functions as a Remote Terminal or Bus Controller
• Interfaces to µP as a Simple Peripheral Unit
• +5V Operation
CIRCUIT TECHNOLOGY
www.aeroflex.com
• Provides 2k by 16 of Double Buffered RAM Storage for Transmit and Receive
Subaddresses
• Pin Programmable for 8-bit or 16-bit Microprocessors
• Full Military (-55°C to +125°C) Temperature Range
General Description
The ACT7005/6 Series provides a complete one package interface between the MIL-STD-1553 bus and all
microprocessor systems. The hybrid provides all data buffers and control registers to function as a Bus
Controller or Remote Terminal. Control of the hybrid by the subsystem is through simple I/O port commands.
Internal hybrid logic removes all critical timing imposed on a typical subsystem, thereby simplifying the
implementation of this interface.
BUS "0"
DUAL
TX/RX
1553
PROTOCOL
BUS "1"
µP
INTERFACE
RAM
INTERRUPTS/
CONTROL
SIGNALS
S
U
B
S
Y
S
T
E
M
8/16
BIT
I/O
ACT7005 / ACT7006
Block Diagram
eroflex Circuit Technology – Data Bus Modules For The Future © SCD7005 REV B 8/2/01
1 page  
Symbol
Parameter
Min Typ Max Units
VDD
Logic Supply
4.5 5.0 5.5
VIH
Input "1"
2.4
VIL Input "0"
0.6
IL
Input I
-450 -600 -900
IIH
Input I
-250 -400 -750
IL
Input I
-50 -200 -800
IIH
Input I
-50 -200 -800
IL
Input I
-25 -125 -400
IIH
Input I
-25 -125 -400
VOH
Output "1"
2.4
VOL Output "0"
0.4
VDD Static I
50
VDD Dynamic I
170
Notes:
1. VDD = 5.5V
A. For RTAD0/1/2/3/4 and RTADPAR with VIL = 0.4V
B. For RTAD0/1/2/3/4 and RTADPAR with VIH = 2.4V
C. FOR BCSTEN WITH VIL = 0.4V, Test 1, 6MHz
D. FOR BCSTEN WITH VIH = 2.4V, Test 1, 6MHz
VDC
V
V
µA
µA
µA
µA
µA
µA
VDC
VDC
mA
mA
Conditions
Note 1A
Note 1B
Note 1C
Note 1D
Note 2A
Note 2B
Note 3A
Note 3B
Note 4A
Note 4B
2. All remaining inputs and I/O
VDD = 5.5V
A. VIL = 0.4V
B. VIH = 2.4V
3. A. VDD = 4.5V and IOH = 3mA
B. VDD = 5.5V and IOL = 3mA
4. VDD = 5.5V
A. Clock Input = 6MHz (45-55% Duty Cycle / TTL Levels), All remaining inputs = VDD,
All Outputs = Open Circuit
B. During a 32 word FIFO to RAM or RAM to FIFO block move.
Aeroflex Circuit Technology
Table 5 – Logic Electrical Characteristics
(Over Full Temperature Range)
5 SCD7005 REV B 8/2/01 Plainview NY (516) 694-6700
5 Page 
parity, and contiguous word checking), but also the
inclusion of a bit by bit comparison of transmitted
data has been added. The added circuitry is used to
insure that the internal functional blocks, encoder,
decoder, and internal control circuitry are functioning
properly. The internal data path can be verified as
fault free by comparing the returned data word with
the supplied data. The most effective data pattern to
accomplish this is HEX AA55, since each bit is
toggled (8 bit internal highway) on a high/low byte
basis. Total time to complete the test is 89
microseconds. TEST ENABLE (bit 9) must remain
low this entire time to ensure proper operation of the
self test.
USE OF A10 AND A10IN
The standard configuration of the ACT7005/6
Series divides the INTERNAL RAM into separate
RECEIVE and TRANSMIT sections. For this
configuration A10 is connected to A10IN. When A10
is high, it addresses the TRANSMIT section; when
low, the RECEIVE sections. A10IN is the address
input to the INTERNAL RAM.
The interface may be configured with one common
section for both RECEIVE and TRANSMIT data. To
configure this, A10 is not connected, and A10IN is
fixed at either a logic high or low. This bit can also be
controlled by the subsystem to provide double
buffering of the contents of common RAM section for
receive and transmit data. If A10 and A10IN are not
directly connected together but gated together, then
no more than 100nsec of propagation delay should
be introduced.
NON-REGISTER OPERATIONAL
COMMANDS
There are six operational commands that are not
register read or write operations. These commands
are summarized in Table 8. The two execute
operations are dependent on the contents of the
OPERATION register. The address codes for all the
operational commands are summarized in the 8 bit
and 16 bit l/O OPERATIONAL tables.
OPTIONAL STATUS WORD CONTROL
Message Error Bit
The ACT7005/6 monitors all receptions for errors
and sets the Message Error Bit as prescribed in
MIL-STD-1553B. The subsystem designer may,
however, exercise the option of monitoring for illegal
commands and forcing the Message Error Bit to be
set.
The word count and subaddress lines for the
current command are valid when INCMD goes low.
The subsystem must then determine whether or not
the word count or subaddress is to be considered
illegal by the RT. If either of them is considered
illegal, the subsystem must produce a
negative-going pulse called MEREQ. The
negative-going edge of MEREQ must occur within
500 nSec of the falling edge of INCMD .
Subsystem Flag and Terminal Flag Bits
The conditions that cause the Subsystem Flag and
Terminal Flag Bits in the Status Word to be reset
may be controlled by the subsystem using the
ENABLE, BIT DECODE, NEXT STATUS, and
STATUS UPDATE inputs. If ENABLE is inactive
(high), then the Terminal Flag and Subsystem Flag
behavior is the same as described below: (i.e. the
other three option lines are disabled).
Subsystem Flag Bit: This bit is reset to logic
zero by a power up initialization or the servicing of
a legal mode command to reset the remote
terminal (code 01000).
This bit shall be set in the current status register
if the subsystem error line, SSERR, from the
subsystem ever goes active low. This bit shall
also be set if an RT/subsystem handshaking
failure occurs. This bit, once set, shall be
repeatedly set until the detected error condition is
known to be no longer present.
Terminal Flag Bit: This bit is reset to logic zero
by a power up initialization or the servicing of a
legal mode command to reset the remote
terminal (code 01000). This bit can be set to logic
one in the current status register in four possible
ways:
a) If the RX detects any message encoding
or content error in the terminals
transmission. A loop test failure, LTFAIL,
will be signalled which shall cause the
Terminal Flag to be set and the
transmission aborted.
b) If a transmitter timeout occurs while the
terminal is transmitting.
c) If a remote terminal self test fails.
d) If there is a parity error in the hard wired
address to the RX chip.
This bit, once set, shall be repeatedly set until
the detected error condition is known to be no
longer present. The transmission of this bit as a
logic one can be inhibited by a legal mode
command to inhibit terminal flag bit (code 00110).
Similarly, this inhibit can be removed by a mode
command to override inhibit terminal flag bit
(code 00111), a power up initialization or a legal
mode command to reset remote terminal (code
01000).
If ENABLE is held low, then the three options
Aeroflex Circuit Technology
11 SCD7005 REV B 8/2/01 Plainview NY (516) 694-6700
11 Page | ||
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| PDF Descargar | [ Datasheet 7006.PDF ] | |
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