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74AC648 반도체 회로 부품 판매점

Octal Transceiver/Register with 3-STATE Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74AC648 데이터시트, 핀배열, 회로
November 1988
Revised August 2000
74AC648
Octal Transceiver/Register with 3-STATE Outputs
General Description
The AC648 consists of registered bus transceiver circuits,
with outputs, D-type flip-flops and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B
bus will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). The four fundamental data handling functions
available are illustrated in Figure 1, Figure 2, Figure 3, and
Figure 4.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data transfers
s 3-STATE outputs
s 300 mil slim dual-in-line package
s Outputs source/sink 24 mA
s Inverted data to output
Ordering Code:
Order Number Package Number
Package Description
74AC648SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74AC648SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
www.DataSheet4U.com
IEEE/IEC
Pin Descriptions
Pin Names
A0A7
B0B7
CPAB, CPBA
SAB, SBA
DIR, G
Description
Data Register A Inputs,
Data Register A 3-STATE Outputs
Data Register B Inputs,
Data Register B 3-STATE Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Inputs
FACTis a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010133
www.fairchildsemi.com


74AC648 데이터시트, 핀배열, 회로
Function Table
Inputs
Data I/O (Note 1)
Function
G DIR CPAB CPBA SAB SBA A0–A7 B0–B7
H X H or L H or L X X
Isolation
H X
X X X Input Input Clock An Data into A Register
H X X
XX
Clock Bn Data into B Register
L H X X L X
An to BnReal Time (Transparent Mode)
LH
X L X Input Output Clock An Data into A Register
L H H or L X H X
L H
XHX
A Register to Bn (Stored Mode)
Clock An Data into A Register and Output to Bn
L L X X X L
Bn to An Real Time (Transparent Mode)
LLX
X L Output Input Clock Bn Data into B Register
L L X H or L X H
L L X
XH
B Register to An (Stored Mode)
Clock Bn Data into B Register and Output to An
H = HIGH Voltage Level
L = LOW Voltage Level
X = Irrelevant
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
Real Time Transfer
A-Bus to B-Bus
Real Time Transfer
B-Bus to A-Bus
FIGURE 1.
Storage from
Bus to Register
FIGURE 2.
Transfer from
Register to Bus
FIGURE 3.
FIGURE 4.
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74AC648 transceiver

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74AC646

Octal Transceiver/Register with 3-STATE Outputs - Fairchild Semiconductor



74AC648

Octal Transceiver/Register with 3-STATE Outputs - Fairchild Semiconductor