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PDF 74ABT899A Data sheet ( Hoja de datos )
| Número de pieza | 74ABT899A | |
| Descripción | 9-bit dual latch transceiver with 8-bit parity generator/checker 3-State | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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November 1992
Revised January 1999
74ABT899
9-Bit Latchable Transceiver
with Parity Generator/Checker
General Description
The ABT899 is a 9-bit to 9-bit parity transceiver with trans-
parent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction.
The ABT899 features independent latch enables for the A-
to-B direction and the B-to-A direction, a select pin for
ODD/EVEN parity, and separate error signal output pins for
checking parity.
Features
s Latchable transceiver with output sink of 64 mA
s Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
s Independent latch enables for A-to-B and B-to-A
directions
s Select pin for ODD/EVEN parity
s ERRA and ERRB output pins for parity checking
s Ability to simultaneously generate and check parity
s May be used in systems applications in place of the
543 and 280
s May be used in system applications in place of the
657 and 373 (no need to change T/R to check parity)
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and
250 pF loads
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
s Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number Package Number
Package Description
74ABT899CSC
M28B
28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body
74ABT899CMSA
MSA28
28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT899CQC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignment
for PLCC
Pin Assignment for
SOIC and SSOP
© 1999 Fairchild Semiconductor Corporation DS011509.prf
www.fairchildsemi.com
1 page  
DC Electrical Characteristics
(PLCC package)
Symbol
Parameter
Conditions
Min Typ Max Units VCC CL = 50 pF, RL = 500Ω
VOLP
Quiet Output Maximum Dynamic VOL
0.8 1.1 V 5.0 TA = 25°C (Note 6)
VOLV
Quiet Output Minimum Dynamic VOL
−1.3 −0.8
V 5.0 TA = 25°C (Note 6)
VOHV
Minimum HIGH Level Dynamic Output Voltage
2.5
3.0
V 5.0 TA = 25°C (Note 8)
VIHD
Minimum HIGH Level Dynamic Input Voltage
2.2
1.8
V 5.0 TA = 25°C (Note 7)
VILD Maximum LOW Level Dynamic Input Voltage
0.8 0.5 V 5.0 TA = 25°C (Note 7)
Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
Note 8: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and PLCC Package)
Symbol
Parameter
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLHtPHL
Propagation Delay
An, to Bn
Propagation Delay
An, Bn to BPAR, APAR
Propagation Delay
An, Bn to ERRA, ERRB
Propagation Delay
APAR, BPAR to ERRA, ERRB
Propagation Delay
ODD/EVEN to APAR, BPAR
Propagation Delay
ODD/EVEN to ERRA, ERRB
Propagation Delay
SEL to APAR, BPAR
Propagation Delay
LEA, LEB to Bn, An
Propagation Delay
LEA, LEB to BPAR, APAR
Generate Mode
Propagation Delay
LEA, LEB to BPAR, APAR,
Feed Thru Mode
Propagation Delay
LEA, LEB to ERRA, ERRB
Output Enable Time
GBA or GAB to An,
APAR or Bn, BPAR
Output Disable Time
GBA or GAB to An,
APAR or Bn, BPAR
Propagation Delay
APAR to BPAR, BPAR to APAR
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Typ Max
1.5 3.0 4.8
1.5 3.5 4.8
2.5 5.9 9.2
2.5 5.8 9.2
2.5 5.4 8.5
2.5 5.4 8.5
1.5 3.7 6.0
1.5 3.7 6.0
2.0 4.4 6.9
2.0 4.4 6.9
1.8 4.0 6.0
1.8 4.0 6.0
1.5 3.8 6.0
1.5 3.8 6.0
1.5 3.2 4.6
1.5 3.2 4.6
2.5 5.9 8.8
2.5 5.7 8.8
1.5 3.6 5.1
1.5 3.6 5.1
1.6 5.4 8.4
1.6 5.4 8.4
1.5 3.6 6.0
1.5 3.4 6.0
1.0 4.0 6.0
1.0 3.3 6.0
1.5 3.3 5.4
1.5 3.8 5.4
TA = −40°C to +85°C
VCC = 4.5V–5.5V
CL = 50 pF
Min Max
1.5 4.8
1.5 4.8
2.5 9.2
2.5 9.2
2.5 8.5
2.5 8.5
1.5 6.0
1.5 6.0
2.0 6.9
2.0 6.9
1.8 6.0
1.8 6.0
1.5 6.0
1.5 6.0
1.5 4.6
1.5 4.6
2.5 8.8
2.5 8.8
1.5 5.1
1.5 5.1
1.6 8.4
1.6 8.4
1.5 6.0
1.5 6.0
1.0 6.0
1.0 6.0
1.5 5.4
1.5 5.4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5 www.fairchildsemi.com
5 Page 
AC Path (Continued)
O/E → BPAR
(O/E → APAR)
APAR → ERRA
(BPAR → ERRB)
FIGURE 5.
FIGURE 6.
ZH, HZ
FIGURE 7.
FIGURE 8.
11
www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74ABT899A.PDF ] | |
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