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NXP Semiconductors |
INTEGRATED CIRCUITS
74ABT833
Octal transceiver with parity
generator/checker (3-State)
Product specification
IC23 Data Handbook
1993 Jun 21
Philips
Semiconductors
Philips Semiconductors
Octal transceiver with parity generator/checker
(3-State)
Product specification
74ABT833
FEATURES
• Low static and dynamic power dissipation with high speed and
high output drive
• Open-collector ERROR output with flag register
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200 V per Machine Model
• Power up/down 3-State
• Live insertion/extraction permitted
DESCRIPTION
The 74ABT833 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT833 is an octal transceiver with a parity
generator/checker and is intended for bus-oriented applications.
When Output Enable A (OEA) is High, it will place the A outputs in a
high impedance state. Output Enable B (OEB) controls the B
outputs in the same way.
The parity generator creates an odd parity output (PARITY) when
OEB is Low. When OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a storage register. If a
Low-to-High transition happens at the clock input (CP), the error
data is stored in the register and the Open-collector error flag
(ERROR) will go Low. The error flag register is cleared with a Low
pulse on the CLEAR input.
If both OEA and OEB are Low, data will flow from the A bus to the B
bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
tPLH
tPHL
CIN
CI/O
ICCZ
Propagation delay
An to Bn or Bn to An
Propagation delay
An to PARITY
Input capacitance
I/O capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled;
VO = 0V or VCC
Outputs disabled; VCC =5.5V
TYPICAL
3.4
7.4
4
7
50
UNIT
ns
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT833 N
74ABT833 D
74ABT833 DB
74ABT833 PW
NORTH AMERICA
74ABT833 N
74ABT833 D
74ABT833 DB
74ABT833PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
OEA 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
ERROR 10
CLEAR 11
GND 12
24 VCC
23 B0
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 PARITY
14 OEB
13 CP
TOP VIEW
SA00212
PIN DESCRIPTION
SYMBOL PIN NUMBER
A0 – A7
2, 3, 4, 5,
6, 7, 8, 9
B0 – B7
23, 22, 21, 20,
19, 18, 17, 16
OEA
1
OEB
PARITY
ERROR
CLEAR
CP
GND
VCC
14
15
10
11
13
12
24
NAME AND FUNCTION
A port 3-State inputs/outputs
B port 3-State inputs/outputs
Enables the A outputs when
Low
Enables the B outputs when
Low
Parity output/input
Error output (open collector)
Clears the error flag register
when Low
Clock input
Ground (0V)
Positive supply voltage
1993 Jun 21
2 853–1619 10087
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