파트넘버.co.kr 74ABT543CMTC 데이터시트 PDF


74ABT543CMTC 반도체 회로 부품 판매점

Octal Registered Transceiver with 3-STATE Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74ABT543CMTC 데이터시트, 핀배열, 회로
November 1992
Revised January 1999
74ABT543
Octal Registered Transceiver with 3-STATE Outputs
General Description
The ABT543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow.
Features
s Back-to-back registers for storage
s Bidirectional data path
s A and B outputs have current sourcing capability of 32
mA and current sinking capability of 64 mA
s Separate controls for data flow in each direction
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and 250 pF
loads
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT543CSC
74ABT543CMSA
M24B
MSA24
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT543CMTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Assignment for
SOIC, SSOP and TSSOP
Pin Names
OEAB, OEBA
LEAB, LEBA
CEAB, CEBA
A0–A7
B0–B7
Description
Output Enable Inputs
Latch Enable Inputs
Chip Enable Inputs
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011508.prf
www.fairchildsemi.com


74ABT543CMTC 데이터시트, 핀배열, 회로
Functional Description
The ABT543 contains two sets of D-type latches, with sep-
arate input and output controls for each. For data flow from
A to B, for example, the A to B Enable (CEAB) input must
be low in order to enter data from the A Port or take data
from the B Port as indicated in the Data I/O Control Table.
With CEAB low, a low signal on (LEAB) input makes the A
to B latches transparent; a subsequent low to high transi-
tion of the LEAB line puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With CEAB and OEAB both low, the B output buffers are
active and reflect the data present on the output of the A
latches. Control of data flow from B to A is similar, but using
the CEBA, LEBA and OEBA.
Logic Diagram
Data I/O Control Table
Inputs
CEAB LEAB OEAB
HXX
XHX
LLX
XXH
LXL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Latch Status
Latched
Latched
Transparent
Output Buffers
HIGH Z
HIGH Z
Driving
www.fairchildsemi.com
2




PDF 파일 내의 페이지 : 총 8 페이지

제조업체: Fairchild Semiconductor

( fairchild )

74ABT543CMTC transceiver

데이터시트 다운로드
:

[ 74ABT543CMTC.PDF ]

[ 74ABT543CMTC 다른 제조사 검색 ]




국내 전력반도체 판매점


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877

[ 홈페이지 ]

IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈

( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )

전력반도체 문의 : 010-3582-2743



일반적인 전자부품 판매점


디바이스마트

IC114

엘레파츠

ICbanQ

Mouser Electronics

DigiKey Electronics

Element14


관련 데이터시트


74ABT543CMTC

Octal Registered Transceiver with 3-STATE Outputs - Fairchild Semiconductor