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Fairchild Semiconductor |
October 1993
Revised November 1999
74ABT16646
16-Bit Transceivers and Registers with 3-STATE Outputs
General Description
The ABT16646 consists of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE is Active
LOW. In the isolation mode (control OE HIGH), A data may
be stored in the B register and/or B data may be stored in
the A register.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data
s A and B output sink capability of 64 mA, source
capability of 32 mA
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT16646CSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16646CMTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
A0–A15
B0–B15
CPABn, CPBAn
SABn, SBAn
OEn
DIR
Description
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Input
Direction Control Input
© 1999 Fairchild Semiconductor Corporation DS011644
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Function Table
Inputs
Data I/O (Note 1)
Output Operation Mode
OE1 DIR1 CPAB1 CPBA1 SAB1 SBA1 A0–7
H X H or L H or L X X
H X
X X X Input
H X X
XX
B0–7
Input
Isolation
Clock An Data into A Register
Clock Bn Data Into B Register
L HXX L X
An to Bn—Real Time (Transparent Mode)
L H
X L X Input Output Clock An Data to A Register
L H H or L X H X
L H
XHX
A Register to Bn (Stored Mode)
Clock An Data into A Register and Output to Bn
L L X X X L
Bn to An—Real Time (Transparent Mode)
LLX
X L Output Input Clock Bn Data into B Register
L
L
X H or L X
H
L L X
XH
B Register to An (Stored Mode)
Clock Bn into B Register and Output to An
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15)
and #2 control pins.
Real Time Transfer
A-Bus to B-Bus
Real Time Transfer
B-Bus to A-Bus
FIGURE 1.
Storage from
Bus to Register
FIGURE 2.
Transfer from
Register to Bus
FIGURE 3.
FIGURE 4.
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