파트넘버.co.kr 7429FCT2053ATPY 데이터시트 PDF


7429FCT2053ATPY 반도체 회로 부품 판매점

FAST CMOS OCTAL REGISTERED TRANSCEIVERS



Integrated Device Technology 로고
Integrated Device Technology
7429FCT2053ATPY 데이터시트, 핀배열, 회로
Integrated Device Technology, Inc.
FAST CMOS
OCTAL REGISTERED
TRANSCEIVERS
IDT29FCT52AT/BT/CT/DT
IDT29FCT2052AT/BT/CT
IDT29FCT53AT/BT/CT
FEATURES:
• Common features:
– Low input and output leakage 1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for 29FCT52/29FCT53T:
– A, B, C and D speed grades
– High drive outputs (-15mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
• Features for 29FCT2052T:
– A, B and C speed grades
– Resistor outputs (-15mA IOH, 12mA IOL Com.)
(-12mA IOH, 12mA IOL Mil.)
– Reduced system switching noise
FUNCTIONAL BLOCK DIAGRAM(1)
CPA
CEA
A0
A1
A2
A3
A4
A5
A6
A7
DESCRIPTION:
The IDT29FCT52AT/BT/CT/DT and IDT29FCT53AT/BT/
CT are 8-bit registered transceivers built using an advanced
dual metal CMOS technology. Two 8-bit back-to-back regis-
ters store data flowing in both directions between two bidirec-
tional buses. Separate clock, clock enable and 3-state output
enable signals are provided for each register. Both A outputs
and B outputs are guaranteed to sink 64mA.
The IDT29FCT52AT/BT/CT/DT and IDT29FCT2052AT/BT/
CT are non-inverting options of the IDT29FCT53AT/BT/CT.
The IDT29FCT2052AT/BT/CT has balanced drive outputs
with current limiting resistors. This offers low ground bounce,
minimal undershoot and controlled output fall times-reducing
the need for external series terminating resistors. The
IDT29FCT2052T part is a plug-in replacement for
IDT29FCT52T part.
D0 CE CP Q0
D1 Q1
D2 Q2
D3 A Q3
D4 Reg. Q4
D5 Q5
D6 Q6
D7 Q7
OEB
B0
B1
B2
B3
B4
B5
B6
B7
NOTE:
OEA
1. IDT29FCT52T/IDT29FCT2052T function is shown. IDT29FCT53T is
the inverting option.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Q0 D0
Q1 D1
Q2 D2
Q3 B D3
Q4 Reg. D4
Q5 D5
Q6 D6
Q7 CE CP D7
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
6.1
CPB
CEB
2629 drw 01
JUNE 1995
DSC-4224/5
1


7429FCT2053ATPY 데이터시트, 핀배열, 회로
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
PIN CONFIGURATIONS
B7
B6
B5
B4
B3
B2
B1
B0
OEB
CPA
CEA
GND
1 24
2 23
3 22
4 P24-1 21
5 D24-1 20
6
SO24-2
SO24-7*
19
7 SO24-8* 18
8 & 17
9 E24-1 16
10 15
11 14
12 13
Vcc
A7
A6
A5
A4
A3
A2
A1
A0
OEA
CPB
CEB
2629 drw 02
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
* For 29FCT52/29FCT2052AT/BT/CT only
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
B4
B3
B2
NC
B1
B0
OEB
432
5
6
28 27 26
1 25
24
7 23
8
L28-1
22
9 21
10 20
11 19
12 13 14 15 16 17 18
A5
A4
A3
NC
A2
A1
A0
LCC
TOP VIEW
2629 drw 03
PIN DESCRIPTION
Name I/O
Description
A0-7 I/O Eight bidirectional lines carrying the A Register inputs or B Register outputs.
B0-7
CPA
CEA
OEB
CPB
CEB
OEA
I/O Eight bidirectional lines carrying the B Register inputs or A Register outputs.
I Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of
the CPA signal.
I Clock Enable for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition
of the CPA signal. When CEA is HIGH, the A Register holds its contents, regardless of CPA signal transitions.
I Output Enable for the A Register. When OEB is LOW, the A Register outputs are enabled onto the B0-7 lines. When
OEB is HIGH, the B0-7 outputs are in the high-impedance state.
I Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of
the CPB signal.
I Clock Enable for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition
of the CPB signal. When CEB is HIGH, the B Register holds its contents, regardless of CPB signal transitions.
I Output Enable for the B Register. When OEA is LOW, the B Register outputs are enabled onto the A0-7 lines. When
OEA is HIGH, the A0-7 outputs are in the high-impedance state.
2629 tbl 01
6.1 2




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7429FCT2053ATPY transceiver

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