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74ALVT16652 반도체 회로 부품 판매점

2.5V/3.3V 16-bit bus transceiver/register 3-State



NXP Semiconductors 로고
NXP Semiconductors
74ALVT16652 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74ALVT16652
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
Product specification
Supersedes data of 1996 Aug 13
IC23 Data Handbook
1998 Feb 13
Philips
Semiconductors


74ALVT16652 데이터시트, 핀배열, 회로
Philips Semiconductors
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
Product specification
74ALVT16652
FEATURES
16–bit bus interface
5V I/O Compatible
3-State buffers
Output capability: +64mA/-32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5V bus
Latch-up protection exceeds 500mA per JEDEC JC40.2 Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
DESCRIPTION
The 74ALVT16652 is a high-performance BiCMOS product
designed for VCC operation at 2.5V or 3.3V with I/O compatibility up
to 5V. The device can be used as two 8-bit transceivers or one
16-bit transceiver.
Complimentary output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. Select-control (SAB
and SBA) inputs are provided to select whether real-time or stored
data is transferred. A Low-input level selects real-time data, and a
High input level selects stored data. The circuitry used for select
control eliminates the typical decoding glitch that occurs in a
multiplexer during the transition between stored and real-time data.
Data on the A or B bus, or both, can be stored in the internal
flip-flops by Low-to-High transitions at the appropriate clock (CPAB
or CPBA) inputs regardless of the levels on the select-control or
output-enable inputs. When SAB and SBA are in real-time transfer
mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this
configuration, each output reinforces its input. Thus, when all other
data sources to the two sets of bus lines are at high impedance,
each set of bus lines remains at its last level configuration.
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C
TYPICAL
2.5V
3.3V
UNIT
tPLH Propagation delay
tPHL nAx to nBx or nBx to nAx
CIN Input capacitance DIR, OE
CL = 50pF
VI = 0V or VCC
2.0 1.5
2.1 1.6
33
ns
pF
CI/O
ICCZ
I/O pin capacitance
Total supply current
VI/O = 0V or VCC
Outputs disabled
99
40 70
pF
µA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVT16652 DL
74ALVT16652 DGG
NORTH AMERICA
AV16652 DL
AV16652 DGG
DWG NUMBER
SOT371-1
SOT364-1
LOGIC SYMBOL (IEEE/IEC)
56 EN1(BA)
1 EN2(AB)
55 C3
54 G4
2 C5
3 G6
29 EN7(BA)
28 EN8(AB)
30 C9
31 G10
27 C11
26 G12
5
w1 4 3D
52 15
w1 10 9D
42
1 41
7 10 1
5D 6 w1
11D 12 w1
16 2
6
8
9
10
12
13
14
51 16
49 17
48 19
47 20
45 21
44 23
43 24
1 12 8
41
40
38
37
36
34
33
SW00158
1998 Feb 13
2 853-1854 18962




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74ALVT16652

2.5V/3.3V 16-bit bus transceiver/register 3-State - NXP Semiconductors