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74ALVCH32501 반도체 회로 부품 판매점

36-bit universal bus transceiver with direction pin; 5 V tolerant; 3-state



NXP Semiconductors 로고
NXP Semiconductors
74ALVCH32501 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
74ALVCH32501
36-bit universal bus transceiver with
direction pin; 5 V tolerant; 3-state
Product specification
File under Integrated Circuits, IC24
2000 Mar 16


74ALVCH32501 데이터시트, 핀배열, 회로
Philips Semiconductors
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
Product specification
74ALVCH32501
FEATURES
3-state non-inverting outputs for bus oriented
applications
Wide supply voltage range of 1.2 to 3.6 V
Complies with JEDEC standard no. 8-1A
Current drive ±24 mA at 3.0 V
Universal bus transceiver with D-type latches and
D-type flip-flops capable of operating in transparent,
latched or clocked mode
CMOS low power consumption
Direct interface with TTL levels
All inputs have bus-hold circuitry
Output drive capability 50 transmission lines at 85 °C
Plastic fine-pitch ball grid array package.
DESCRIPTION
The 74ALVCH32501 is a high-performance CMOS
product designed for VCC operation at 2.5 and 3.3 V with
I/O compatibility up to 5 V.
Active bus-hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
The 74ALVCH32501 can be used as two 18-bit
transceivers or one 36-bit transceiver featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CPAB and CPBA).
For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When input LEAB is
LOW, the A data is latched if input CPAB is held at a HIGH
or LOW level. If input LEAB is LOW, the A data is stored in
the latch/flip-flop on the LOW-to-HIGH transition of CPAB.
When input OEAB is HIGH, the outputs are active. When
input OEAB is LOW, the outputs are in the high-impedance
state.
Data flow for B-to-A is similar to that of A-to-B, but uses
inputs OEBA, LEBA and CPBA. The output enables are
complimentary (OEAB is active HIGH, and OEBA is active
LOW).
To ensure the high-impedance state during power-up or
power-down, pin OEBA should be tied to VCC through a
pull-up resistor and pin OEAB should be tied to GND
through a pull-down resistor. The minimum value of the
resistor is determined by the current-sinking or
current-sourcing capability of the driver.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.
SYMBOL
PARAMETER
tPHL/tPLH propagation delay An to Bn; Bn to An
CI input capacitance
CI/O input/output capacitance
CPD power dissipation capacitance per latch
CONDITIONS
CL = 30 pF; VCC = 2.5 V
CL = 50 pF; VCC = 3.3 V
VI = GND to VCC; note 1
outputs enabled
outputs disabled
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
TYP.
2.8
3.0
4.0
8.0
UNIT
ns
ns
pF
pF
21 pF
3 pF
2000 Mar 16
2




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74ALVCH32501 transceiver

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74ALVCH32501

36-bit universal bus transceiver with direction pin; 5 V tolerant; 3-state - NXP Semiconductors